diff options
| -rw-r--r-- | llvm/test/CodeGen/AArch64/bool-ext-inc.ll | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/bool-ext-inc.ll b/llvm/test/CodeGen/AArch64/bool-ext-inc.ll new file mode 100644 index 00000000000..7fc451e4d75 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/bool-ext-inc.ll @@ -0,0 +1,29 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s + +define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) { +; CHECK-LABEL: sextbool_add_vector: +; CHECK: // %bb.0: +; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s +; CHECK-NEXT: add v0.4s, v2.4s, v0.4s +; CHECK-NEXT: ret + %c = icmp eq <4 x i32> %c1, %c2 + %b = sext <4 x i1> %c to <4 x i32> + %s = add <4 x i32> %x, %b + ret <4 x i32> %s +} + +define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) { +; CHECK-LABEL: zextbool_sub_vector: +; CHECK: // %bb.0: +; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s +; CHECK-NEXT: movi v1.4s, #1 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: sub v0.4s, v2.4s, v0.4s +; CHECK-NEXT: ret + %c = icmp eq <4 x i32> %c1, %c2 + %b = zext <4 x i1> %c to <4 x i32> + %s = sub <4 x i32> %x, %b + ret <4 x i32> %s +} + |
