diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll | 65 |
3 files changed, 79 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index a356e4d728f..d5665ab67c5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2284,7 +2284,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, } if (bestWidth) { EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); - if (newVT.isRound()) { + if (newVT.isRound() && + shouldReduceLoadWidth(Lod, ISD::NON_EXTLOAD, newVT)) { EVT PtrType = Lod->getOperand(1).getValueType(); SDValue Ptr = Lod->getBasePtr(); if (bestOffset != 0) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index a1b9198f945..9823dd7709d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -667,6 +667,18 @@ bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, EVT OldVT = N->getValueType(0); unsigned OldSize = OldVT.getStoreSizeInBits(); + MemSDNode *MN = cast<MemSDNode>(N); + unsigned AS = MN->getAddressSpace(); + // Do not shrink an aligned scalar load to sub-dword. + // Scalar engine cannot do sub-dword loads. + if (OldSize >= 32 && NewSize < 32 && MN->getAlignment() >= 4 && + (AS == AMDGPUAS::CONSTANT_ADDRESS || + AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT || + (isa<LoadSDNode>(N) && + AS == AMDGPUAS::GLOBAL_ADDRESS && MN->isInvariant())) && + AMDGPUInstrInfo::isUniformMMO(MN->getMemOperand())) + return false; + // Don't produce extloads from sub 32-bit types. SI doesn't have scalar // extloads, so doing one requires using a buffer_load. In cases where we // still couldn't use a scalar load, using the wider load shouldn't really diff --git a/llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll b/llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll new file mode 100644 index 00000000000..ae50d4f18c4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll @@ -0,0 +1,65 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}const_load_no_shrink_dword_to_unaligned_byte: +; GCN: s_load_dword [[LD:s[0-9]+]], +; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013 +define amdgpu_kernel void @const_load_no_shrink_dword_to_unaligned_byte(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %x) { + %ptr = getelementptr i32, i32 addrspace(4)* %in, i32 %x + %load = load i32, i32 addrspace(4)* %ptr, align 4 + %and = and i32 %load, 524288 + %cmp = icmp eq i32 %and, 0 + %sel = select i1 %cmp, i32 0, i32 -1 + store i32 %sel, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: const_load_no_shrink_dword_to_aligned_byte: +; GCN: s_load_dword [[LD:s[0-9]+]], +; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003 +define amdgpu_kernel void @const_load_no_shrink_dword_to_aligned_byte(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %x) { + %ptr = getelementptr i32, i32 addrspace(4)* %in, i32 %x + %load = load i32, i32 addrspace(4)* %ptr, align 4 + %and = and i32 %load, 8 + %cmp = icmp eq i32 %and, 0 + %sel = select i1 %cmp, i32 0, i32 -1 + store i32 %sel, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: global_load_no_shrink_dword_to_unaligned_byte: +; GCN: s_load_dword [[LD:s[0-9]+]], +; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10013 +define amdgpu_kernel void @global_load_no_shrink_dword_to_unaligned_byte(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %x) { + %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %x + %load = load i32, i32 addrspace(1)* %ptr, align 4 + %and = and i32 %load, 524288 + %cmp = icmp eq i32 %and, 0 + %sel = select i1 %cmp, i32 0, i32 -1 + store i32 %sel, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: global_load_no_shrink_dword_to_aligned_byte: +; GCN: s_load_dword [[LD:s[0-9]+]], +; GCN: s_bfe_i32 s{{[0-9]+}}, [[LD]], 0x10003 +define amdgpu_kernel void @global_load_no_shrink_dword_to_aligned_byte(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %x) { + %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %x + %load = load i32, i32 addrspace(1)* %ptr, align 4 + %and = and i32 %load, 8 + %cmp = icmp eq i32 %and, 0 + %sel = select i1 %cmp, i32 0, i32 -1 + store i32 %sel, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: const_load_shrink_dword_to_unaligned_byte: +; GCN: global_load_ushort +define amdgpu_kernel void @const_load_shrink_dword_to_unaligned_byte(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %x) { + %ptr = getelementptr i32, i32 addrspace(4)* %in, i32 %x + %load = load i32, i32 addrspace(4)* %ptr, align 2 + %and = and i32 %load, 524288 + %cmp = icmp eq i32 %and, 0 + %sel = select i1 %cmp, i32 0, i32 -1 + store i32 %sel, i32 addrspace(1)* %out + ret void +} |
