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-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp3
-rw-r--r--llvm/test/CodeGen/PowerPC/altivec-ord.ll17
2 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 685b082a435..1759c0415e5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -487,6 +487,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
+
+ setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
+ setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
}
if (Subtarget->has64BitSupport()) {
diff --git a/llvm/test/CodeGen/PowerPC/altivec-ord.ll b/llvm/test/CodeGen/PowerPC/altivec-ord.ll
new file mode 100644
index 00000000000..6aea8433a1e
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/altivec-ord.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <4 x i16> @test(<4 x float> %f, <4 x float> %g) {
+entry:
+ %r = fcmp ord <4 x float> %f, %g
+ %s = sext <4 x i1> %r to <4 x i16>
+ ret <4 x i16> %s
+}
+
+define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) {
+entry:
+ %r = fcmp one <4 x float> %f, %g
+ %s = sext <4 x i1> %r to <4 x i16>
+ ret <4 x i16> %s
+}
+
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