diff options
6 files changed, 10 insertions, 11 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index 3baa2574fd1..d19463ccb51 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -114,7 +114,7 @@ void WebAssemblyAsmPrinter::EmitFunctionBodyStart() { getTargetStreamer()->emitParam(CurrentFnSym, MFI->getParams()); SmallVector<MVT, 4> ResultVTs; - const Function &F(*MF->getFunction()); + const Function &F = MF->getFunction(); // Emit the function index. if (MDNode *Idx = F.getMetadata("wasm.index")) { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp index a37d6136e44..84246052f60 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp @@ -94,7 +94,7 @@ bool WebAssemblyFrameLowering::needsSPWriteback( const MachineFunction &MF, const MachineFrameInfo &MFI) const { assert(needsSP(MF, MFI)); return MFI.getStackSize() > RedZoneSize || MFI.hasCalls() || - MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); + MF.getFunction().hasFnAttribute(Attribute::NoRedZone); } static void writeSPToMemory(unsigned SrcReg, MachineFunction &MF, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp index 4f3ae57733e..9f40d35689a 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp @@ -48,9 +48,8 @@ public: } bool runOnMachineFunction(MachineFunction &MF) override { - ForCodeSize = - MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) || - MF.getFunction()->hasFnAttribute(Attribute::MinSize); + ForCodeSize = MF.getFunction().hasFnAttribute(Attribute::OptimizeForSize) || + MF.getFunction().hasFnAttribute(Attribute::MinSize); Subtarget = &MF.getSubtarget<WebAssemblySubtarget>(); return SelectionDAGISel::runOnMachineFunction(MF); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index c6f1a663a4f..299009fa667 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -214,7 +214,7 @@ LowerFPToInt( int64_t Limit = Int64 ? INT64_MIN : INT32_MIN; int64_t Substitute = IsUnsigned ? 0 : Limit; double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit; - auto &Context = BB->getParent()->getFunction()->getContext(); + auto &Context = BB->getParent()->getFunction().getContext(); Type *Ty = Float64 ? Type::getDoubleTy(Context) : Type::getFloatTy(Context); const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -438,7 +438,7 @@ bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT, static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *msg) { MachineFunction &MF = DAG.getMachineFunction(); DAG.getContext()->diagnose( - DiagnosticInfoUnsupported(*MF.getFunction(), msg, DL.getDebugLoc())); + DiagnosticInfoUnsupported(MF.getFunction(), msg, DL.getDebugLoc())); } // Test whether the given calling convention is supported. @@ -697,7 +697,7 @@ SDValue WebAssemblyTargetLowering::LowerFormalArguments( // Record the number and types of results. SmallVector<MVT, 4> Params; SmallVector<MVT, 4> Results; - ComputeSignatureVTs(*MF.getFunction(), DAG.getTarget(), Params, Results); + ComputeSignatureVTs(MF.getFunction(), DAG.getTarget(), Params, Results); for (MVT VT : Results) MFI->addResult(VT); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp index 8880539804c..4a93d4810c7 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp @@ -43,7 +43,7 @@ WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const { if (const auto *FuncTy = dyn_cast<FunctionType>(Global->getValueType())) { const MachineFunction &MF = *MO.getParent()->getParent()->getParent(); const TargetMachine &TM = MF.getTarget(); - const Function &CurrentFunc = *MF.getFunction(); + const Function &CurrentFunc = MF.getFunction(); SmallVector<wasm::ValType, 4> Returns; SmallVector<wasm::ValType, 4> Params; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index e5e9f9d5f61..2bdba96ab67 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -107,12 +107,12 @@ static void ConvertImplicitDefToConstZero(MachineInstr *MI, } else if (RegClass == &WebAssembly::F32RegClass) { MI->setDesc(TII->get(WebAssembly::CONST_F32)); ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue( - Type::getFloatTy(MF.getFunction()->getContext()))); + Type::getFloatTy(MF.getFunction().getContext()))); MI->addOperand(MachineOperand::CreateFPImm(Val)); } else if (RegClass == &WebAssembly::F64RegClass) { MI->setDesc(TII->get(WebAssembly::CONST_F64)); ConstantFP *Val = cast<ConstantFP>(Constant::getNullValue( - Type::getDoubleTy(MF.getFunction()->getContext()))); + Type::getDoubleTy(MF.getFunction().getContext()))); MI->addOperand(MachineOperand::CreateFPImm(Val)); } else { llvm_unreachable("Unexpected reg class"); |
