diff options
79 files changed, 73 insertions, 132 deletions
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h index a04e9f0a7a8..778f72c06e6 100644 --- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h +++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h @@ -381,8 +381,6 @@ struct MachineFunction { StringRef Name; unsigned Alignment = 0; bool ExposesReturnsTwice = false; - // MachineFunctionProperties - bool AllVRegsAllocated = false; // GISel MachineFunctionProperties. bool Legalized = false; bool RegBankSelected = false; @@ -407,7 +405,6 @@ template <> struct MappingTraits<MachineFunction> { YamlIO.mapRequired("name", MF.Name); YamlIO.mapOptional("alignment", MF.Alignment); YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); - YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated); YamlIO.mapOptional("legalized", MF.Legalized); YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); YamlIO.mapOptional("selected", MF.Selected); diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index f1d51a572fb..e6807375c35 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -79,7 +79,6 @@ struct MachineFunctionInfo { /// Each of these has checking code in the MachineVerifier, and passes can /// require that a property be set. class MachineFunctionProperties { - // TODO: Add MachineVerifier checks for AllVRegsAllocated // Possible TODO: Allow targets to extend this (perhaps by allowing the // constructor to specify the size of the bit vector) // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be @@ -100,8 +99,7 @@ public: // that affect the values in registers, for example by the register // scavenger. // When this property is clear, liveness is no longer reliable. - // AllVRegsAllocated: All virtual registers have been allocated; i.e. all - // register operands are physical registers. + // NoVRegs: The machine function does not use any virtual registers. // Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic // instructions have been legalized; i.e., all instructions are now one of: // - generic and always legal (e.g., COPY) @@ -120,7 +118,7 @@ public: IsSSA, NoPHIs, TracksLiveness, - AllVRegsAllocated, + NoVRegs, Legalized, RegBankSelected, Selected, diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp index 2f173f84d73..400413be5b6 100644 --- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp +++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp @@ -172,7 +172,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/CodeGen/FuncletLayout.cpp b/llvm/lib/CodeGen/FuncletLayout.cpp index b16f81c728d..d61afad4db5 100644 --- a/llvm/lib/CodeGen/FuncletLayout.cpp +++ b/llvm/lib/CodeGen/FuncletLayout.cpp @@ -30,7 +30,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index 9cddcfa4330..1cca1f83dff 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -203,7 +203,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index 31d6bd0b6dc..f9e3155c049 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -129,7 +129,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp index 4ff88d52810..4986895ba03 100644 --- a/llvm/lib/CodeGen/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues.cpp @@ -217,7 +217,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } /// Print to ostream with a message. diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 31bb1dccb88..4e9cd8b4493 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -312,6 +312,10 @@ void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) { Properties.set(MachineFunctionProperties::Property::IsSSA); else Properties.clear(MachineFunctionProperties::Property::IsSSA); + + const MachineRegisterInfo &MRI = MF.getRegInfo(); + if (MRI.getNumVirtRegs() == 0) + Properties.set(MachineFunctionProperties::Property::NoVRegs); } bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { @@ -324,8 +328,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { if (YamlMF.Alignment) MF.setAlignment(YamlMF.Alignment); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); - if (YamlMF.AllVRegsAllocated) - MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated); if (YamlMF.Legalized) MF.getProperties().set(MachineFunctionProperties::Property::Legalized); diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 1cd4eb9d0ea..7b9baa7db0a 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -174,8 +174,6 @@ void MIRPrinter::print(const MachineFunction &MF) { YamlMF.Name = MF.getName(); YamlMF.Alignment = MF.getAlignment(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); - YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::AllVRegsAllocated); YamlMF.Legalized = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Legalized); diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index bf61ee04f9b..92d043df26b 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -56,7 +56,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index c12f8094dc1..f5c8147d859 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -57,10 +57,10 @@ void MachineFunctionInitializer::anchor() {} static const char *getPropertyName(MachineFunctionProperties::Property Prop) { typedef MachineFunctionProperties::Property P; switch(Prop) { - case P::AllVRegsAllocated: return "AllVRegsAllocated"; case P::IsSSA: return "IsSSA"; case P::Legalized: return "Legalized"; case P::NoPHIs: return "NoPHIs"; + case P::NoVRegs: return "NoVRegs"; case P::RegBankSelected: return "RegBankSelected"; case P::Selected: return "Selected"; case P::TracksLiveness: return "TracksLiveness"; diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index d75b90f96a5..f0ab4c3816c 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -314,15 +314,12 @@ void MachineVerifier::verifySlotIndexes() const { void MachineVerifier::verifyProperties(const MachineFunction &MF) { // If a pass has introduced virtual registers without clearing the - // AllVRegsAllocated property (or set it without allocating the vregs) + // NoVRegs property (or set it without allocating the vregs) // then report an error. if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::AllVRegsAllocated) && - MRI->getNumVirtRegs()) { - report( - "Function has AllVRegsAllocated property but there are VReg operands", - &MF); - } + MachineFunctionProperties::Property::NoVRegs) && + MRI->getNumVirtRegs()) + report("Function has NoVRegs property but there are VReg operands", &MF); } unsigned MachineVerifier::verify(MachineFunction &MF) { diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp index 32468c90b86..ad9166f1ed2 100644 --- a/llvm/lib/CodeGen/PatchableFunction.cpp +++ b/llvm/lib/CodeGen/PatchableFunction.cpp @@ -32,7 +32,7 @@ struct PatchableFunction : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 3fce307f3dd..6081916a6a8 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -98,7 +98,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } bool runOnMachineFunction(MachineFunction &Fn) override; diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp index a167b3d1c91..6ddf9537a71 100644 --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -80,7 +80,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties MFP; if (UsesCalleeSaves) - MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated); + MFP.set(MachineFunctionProperties::Property::NoVRegs); return MFP; } diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index febb29c9dd4..ab743099683 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -165,7 +165,7 @@ namespace { MachineFunctionProperties getSetProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp index 86dab766508..546e63247d0 100644 --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -63,7 +63,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } /// \brief Calculate the liveness information for the given machine function. diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index fcba8add32c..57aa740e877 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -177,7 +177,7 @@ public: bool runOnMachineFunction(MachineFunction&) override; MachineFunctionProperties getSetProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } // end anonymous namespace diff --git a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp index 510cdba5faf..847eafce5bd 100644 --- a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp +++ b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp @@ -90,7 +90,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index 4dbc1d77fe1..d30bea7565f 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -122,7 +122,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp index e19187e79d4..268b301c3ea 100644 --- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp @@ -177,7 +177,7 @@ struct AArch64CollectLOH : public MachineFunctionPass { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 8681b7ca115..e238c6dde40 100644 --- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -46,7 +46,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index dc07af6f5ad..4f3a6ac69b1 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -162,7 +162,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index 9e916ef8dd7..da3d6a0daee 100644 --- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -54,7 +54,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { return "AArch64 Redundant Copy Elimination"; diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index cc65e9334ff..fd679f0f6b0 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -197,7 +197,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 062f7c6cb52..9ce92f0c415 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -53,7 +53,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 5eb6c8ba301..fff6c0edb78 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -95,7 +95,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp b/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp index 73dcb9641b6..fd67ebf26bb 100644 --- a/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp +++ b/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp @@ -29,7 +29,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index 0c705555163..01736be78cc 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -38,7 +38,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index d35a1898bae..5a6089396ca 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -148,7 +148,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp index 63af9cbfbcd..03b9c631578 100644 --- a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -51,7 +51,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index dc0357223f7..ac6b0e8795a 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -85,7 +85,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index 6665e924baa..acb1ef2d292 100644 --- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -47,7 +47,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 644c643d066..88a9e266f3e 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -182,7 +182,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index bb9256db4b4..2b71cc1edcd 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -51,7 +51,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 14f324628f1..bc8eefce707 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -85,7 +85,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp index efd28350183..a9206bd63f3 100644 --- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -57,7 +57,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } static char ID; diff --git a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp index 5ea1c5d19a5..d15d6942797 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -49,7 +49,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index adc52b206eb..1a7c4b30797 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -80,7 +80,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp index 7b106547d60..e0798bf4482 100644 --- a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -60,7 +60,7 @@ struct Filler : public MachineFunctionPass { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void insertDefsUses(MachineBasicBlock::instr_iterator MI, diff --git a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp index 64e784bf0d4..0d66a785db4 100644 --- a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -69,7 +69,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp index 8bb695bc364..cb08042629e 100644 --- a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp +++ b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -41,7 +41,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index cbc5e4bdd4e..c6f5e6bec20 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -364,7 +364,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs); diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index eb0d3142bec..f5b629846ae 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -213,7 +213,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp index 10022ba6068..4a1b5d70f80 100644 --- a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp +++ b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp @@ -76,7 +76,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/Mips/MipsLongBranch.cpp b/llvm/lib/Target/Mips/MipsLongBranch.cpp index c745e3da222..dfb08101956 100644 --- a/llvm/lib/Target/Mips/MipsLongBranch.cpp +++ b/llvm/lib/Target/Mips/MipsLongBranch.cpp @@ -74,7 +74,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp index a7352a9074b..fec0917b05b 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -48,7 +48,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp index fcd2f50e1e3..cad4f4f2289 100644 --- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp +++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -196,7 +196,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp index 944f3551279..4b55c1ce989 100644 --- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp @@ -64,7 +64,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void insertCallDefsUses(MachineBasicBlock::iterator MI, diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index 27350b88554..89edf535fe0 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -66,7 +66,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp index a24d47d2d16..98f2124209a 100644 --- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -140,7 +140,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp index 7f26a3519e5..d36f051a1cc 100644 --- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -37,7 +37,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 1d21f2b33fd..3aa25932f84 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -196,7 +196,7 @@ void WebAssemblyPassConfig::addPostRegAlloc() { // Has no asserts of its own, but was not written to handle virtual regs. disablePass(&ShrinkWrapID); - // These functions all require the AllVRegsAllocated property. + // These functions all require the NoVRegs property. disablePass(&MachineCopyPropagationID); disablePass(&PostRASchedulerID); disablePass(&FuncletLayoutID); diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp index 093fed7276f..ca94bf094d5 100644 --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -51,7 +51,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp index 90e758dc2e0..281d2b3cc5f 100644 --- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp +++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp @@ -125,7 +125,7 @@ public: MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index 013ee249a60..b0ad33619eb 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -95,7 +95,7 @@ public: // This pass runs after regalloc and doesn't support VReg operands. MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 55c1bff2bc1..fcea6993d97 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -78,7 +78,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { return "X86 FP Stackifier"; } diff --git a/llvm/lib/Target/X86/X86PadShortFunction.cpp b/llvm/lib/Target/X86/X86PadShortFunction.cpp index 62a9aafc2cf..cd70511b31f 100644 --- a/llvm/lib/Target/X86/X86PadShortFunction.cpp +++ b/llvm/lib/Target/X86/X86PadShortFunction.cpp @@ -57,7 +57,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp index 9320e1e2226..df165be63e6 100644 --- a/llvm/lib/Target/X86/X86VZeroUpper.cpp +++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp @@ -40,7 +40,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override {return "X86 vzeroupper inserter";} diff --git a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp index 92cfc40e047..c6e6214d958 100644 --- a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -29,7 +29,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { diff --git a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir index 65d8acb3578..88a4b2c0cd9 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir @@ -28,7 +28,6 @@ name: promote-load-from-store alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%x0' } @@ -83,7 +82,6 @@ body: | name: store-pair alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%x0' } diff --git a/llvm/test/CodeGen/AArch64/movimm-wzr.mir b/llvm/test/CodeGen/AArch64/movimm-wzr.mir index c26643ed106..c6bfcf121a3 100644 --- a/llvm/test/CodeGen/AArch64/movimm-wzr.mir +++ b/llvm/test/CodeGen/AArch64/movimm-wzr.mir @@ -15,7 +15,6 @@ name: test_mov_0 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false frameInfo: isFrameAddressTaken: false diff --git a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir index 144961b7ac9..0e6f80bfb48 100644 --- a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -79,7 +79,6 @@ name: f alignment: 1 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%r0' } diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir b/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir index 83a1046357c..780b9cedf7f 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir @@ -14,7 +14,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: %bb.1, %bb.2 diff --git a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir index 0ad0e9d568b..7e7b318009a 100644 --- a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir @@ -33,7 +33,6 @@ name: test_tlsdesc_callseq_length alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: false liveins: - { reg: '%w0' } diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir index 90f2f3c0999..cb552e5cab3 100644 --- a/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir +++ b/llvm/test/CodeGen/MIR/AArch64/machine-dead-copy.mir @@ -13,9 +13,8 @@ # CHECK-LABEL: name: copyprop1 # CHECK: bb.0: # CHECK-NOT: %w20 = COPY -name: copyprop1 -allVRegsAllocated: true -body: | +name: copyprop1 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -28,9 +27,8 @@ body: | # CHECK-LABEL: name: copyprop2 # CHECK: bb.0: # CHECK: %w20 = COPY -name: copyprop2 -allVRegsAllocated: true -body: | +name: copyprop2 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -43,9 +41,8 @@ body: | # CHECK-LABEL: name: copyprop3 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop3 -allVRegsAllocated: true -body: | +name: copyprop3 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -58,9 +55,8 @@ body: | # CHECK-LABEL: name: copyprop4 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop4 -allVRegsAllocated: true -body: | +name: copyprop4 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w0 diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index 7a0d2989d56..74ea7c63d4b 100644 --- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -90,7 +90,6 @@ name: f alignment: 1 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%r0' } diff --git a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir index a83c53e57cd..09bc49c508a 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir @@ -10,7 +10,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir index e9f2966688c..5056a05ed1f 100644 --- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -175,7 +175,6 @@ name: test0a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -220,7 +219,6 @@ body: | name: test0b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -263,7 +261,6 @@ body: | name: test1a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -310,7 +307,6 @@ body: | name: test1b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -357,7 +353,6 @@ body: | name: test2a alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -404,7 +399,6 @@ body: | name: test2b alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -451,7 +445,6 @@ body: | name: test3 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -498,7 +491,6 @@ body: | name: test4 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -609,7 +601,6 @@ body: | name: testBB alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: gpr } diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index a49251bde35..cf6ab35d8db 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -44,7 +44,6 @@ name: mm_update_next_owner alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%x3' } diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index 45ff51dc958..bd0e7383d52 100644 --- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -26,7 +26,6 @@ name: test1 alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true frameInfo: isFrameAddressTaken: false diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index d4b83b9a499..bba3e152699 100644 --- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -32,7 +32,6 @@ name: fn1 alignment: 2 exposesReturnsTwice: false -allVRegsAllocated: false tracksRegLiveness: true registers: - { id: 0, class: g8rc } diff --git a/llvm/test/CodeGen/X86/eflags-copy-expansion.mir b/llvm/test/CodeGen/X86/eflags-copy-expansion.mir index 43d4e3b7f57..36044b4d205 100644 --- a/llvm/test/CodeGen/X86/eflags-copy-expansion.mir +++ b/llvm/test/CodeGen/X86/eflags-copy-expansion.mir @@ -19,7 +19,6 @@ --- name: foo -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/CodeGen/X86/fixup-bw-copy.mir b/llvm/test/CodeGen/X86/fixup-bw-copy.mir index e39688fe7db..bbb60ad4b59 100644 --- a/llvm/test/CodeGen/X86/fixup-bw-copy.mir +++ b/llvm/test/CodeGen/X86/fixup-bw-copy.mir @@ -38,7 +38,6 @@ --- name: test_movb_killed -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -54,7 +53,6 @@ body: | --- name: test_movb_impuse -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -70,7 +68,6 @@ body: | --- name: test_movb_impdef_gr64 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -86,7 +83,6 @@ body: | --- name: test_movb_impdef_gr32 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -102,7 +98,6 @@ body: | --- name: test_movb_impdef_gr16 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -118,7 +113,6 @@ body: | --- name: test_movw_impdef_gr32 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -134,7 +128,6 @@ body: | --- name: test_movw_impdef_gr64 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index b2b7acaf5da..16a1a1ca2dc 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -85,7 +85,6 @@ name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -128,7 +127,6 @@ body: | --- name: imp_null_check_with_bitwise_op_1 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -176,7 +174,6 @@ body: | name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -220,7 +217,6 @@ body: | name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/X86/machine-copy-prop.mir b/llvm/test/CodeGen/X86/machine-copy-prop.mir index c2cb4ceb7fb..225a43061c9 100644 --- a/llvm/test/CodeGen/X86/machine-copy-prop.mir +++ b/llvm/test/CodeGen/X86/machine-copy-prop.mir @@ -25,7 +25,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -43,7 +42,6 @@ body: | # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -61,7 +59,6 @@ body: | # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill2 -allVRegsAllocated: true body: | bb.0: %ax = COPY %di @@ -79,7 +76,6 @@ body: | # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -96,7 +92,6 @@ body: | # CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -113,7 +108,6 @@ body: | # CHECK-NOT: %rax = COPY %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -132,7 +126,6 @@ body: | # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -150,7 +143,6 @@ body: | # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop1 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -168,7 +160,6 @@ body: | # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -186,7 +177,6 @@ body: | # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop3 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -203,7 +193,6 @@ body: | # CHECK-NEXT: %rax = COPY %rip # CHECK-NEXT: NOOP implicit %rax name: nocopyprop4 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rip @@ -219,7 +208,6 @@ body: | # CHECK-NEXT: %rip = COPY %rax # CHECK-NEXT: %rip = COPY %rax name: nocopyprop5 -allVRegsAllocated: true body: | bb.0: %rip = COPY %rax diff --git a/llvm/test/CodeGen/X86/pr27681.mir b/llvm/test/CodeGen/X86/pr27681.mir index 9473a21d732..3e931b182e4 100644 --- a/llvm/test/CodeGen/X86/pr27681.mir +++ b/llvm/test/CodeGen/X86/pr27681.mir @@ -11,7 +11,6 @@ --- # CHECK-LABEL: main name: main -allVRegsAllocated: true tracksRegLiveness: true frameInfo: stackSize: 52 diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir index ea898ec1c0c..ceaec8d8568 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -157,7 +157,6 @@ name: add alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir index 920d6538ab9..31d39dce3ab 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir @@ -159,7 +159,6 @@ name: main alignment: 4 exposesReturnsTwice: false -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } |
