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-rw-r--r--llvm/lib/Target/AArch64/AArch64.td6
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.td4
-rw-r--r--llvm/lib/Target/AArch64/AArch64Subtarget.h4
-rw-r--r--llvm/lib/Target/AArch64/AArch64SystemOperands.td2
-rw-r--r--llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp2
-rw-r--r--llvm/test/MC/AArch64/armv8.5a-predres-error.s (renamed from llvm/test/MC/AArch64/armv8.5a-predctrl-error.s)2
-rw-r--r--llvm/test/MC/AArch64/armv8.5a-predres.s (renamed from llvm/test/MC/AArch64/armv8.5a-predctrl.s)10
-rw-r--r--llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt (renamed from llvm/test/MC/Disassembler/AArch64/armv8.5a-predctrl.txt)4
8 files changed, 17 insertions, 17 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index e6da78d3545..03d28303a2f 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -312,8 +312,8 @@ def FeatureSB : SubtargetFeature<"sb", "HasSB",
def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
"true", "Enable Speculative Store Bypass Safe bit" >;
-def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
- "Enable execution and data prediction invalidation instructions" >;
+def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
+ "Enable v8.5a execution and data prediction invalidation instructions" >;
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
"true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
@@ -352,7 +352,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
- FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
+ FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
FeatureBranchTargetId]
>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 67a2095c65a..22dd198ab86 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -116,8 +116,8 @@ def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
def HasSB : Predicate<"Subtarget->hasSB()">,
AssemblerPredicate<"FeatureSB", "sb">;
-def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
- AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
+def HasPredRes : Predicate<"Subtarget->hasPredRes()">,
+ AssemblerPredicate<"FeaturePredRes", "predres">;
def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
def HasBTI : Predicate<"Subtarget->hasBTI()">,
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index e94a044c09c..f2ad4b504ac 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -128,7 +128,7 @@ protected:
bool HasSpecRestrict = false;
bool HasSSBS = false;
bool HasSB = false;
- bool HasPredCtrl = false;
+ bool HasPredRes = false;
bool HasCCDP = false;
bool HasBTI = false;
bool HasRandGen = false;
@@ -357,7 +357,7 @@ public:
bool hasSpecRestrict() const { return HasSpecRestrict; }
bool hasSSBS() const { return HasSSBS; }
bool hasSB() const { return HasSB; }
- bool hasPredCtrl() const { return HasPredCtrl; }
+ bool hasPredRes() const { return HasPredRes; }
bool hasCCDP() const { return HasCCDP; }
bool hasBTI() const { return HasBTI; }
bool hasRandGen() const { return HasRandGen; }
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 60d48e4d99d..a804fb11175 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -501,7 +501,7 @@ class PRCTX<string name, bits<4> crm> : SearchableTable {
code Requires = [{ {} }];
}
-let Requires = [{ {AArch64::FeaturePredCtrl} }] in {
+let Requires = [{ {AArch64::FeaturePredRes} }] in {
def : PRCTX<"RCTX", 0b0011>;
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 88766592e31..6cc9b67e4d2 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2826,7 +2826,7 @@ static const struct Extension {
{"simd", {AArch64::FeatureNEON}},
{"ras", {AArch64::FeatureRAS}},
{"lse", {AArch64::FeatureLSE}},
- {"predctrl", {AArch64::FeaturePredCtrl}},
+ {"predres", {AArch64::FeaturePredRes}},
{"ccdp", {AArch64::FeatureCacheDeepPersist}},
{"mte", {AArch64::FeatureMTE}},
{"tlb-rmi", {AArch64::FeatureTLB_RMI}},
diff --git a/llvm/test/MC/AArch64/armv8.5a-predctrl-error.s b/llvm/test/MC/AArch64/armv8.5a-predres-error.s
index 0fd49b02bee..295252d0f67 100644
--- a/llvm/test/MC/AArch64/armv8.5a-predctrl-error.s
+++ b/llvm/test/MC/AArch64/armv8.5a-predres-error.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predctrl < %s 2>&1| FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predres < %s 2>&1| FileCheck %s
cfp rctx
dvp rctx
diff --git a/llvm/test/MC/AArch64/armv8.5a-predctrl.s b/llvm/test/MC/AArch64/armv8.5a-predres.s
index af7dda76862..4bab34769ac 100644
--- a/llvm/test/MC/AArch64/armv8.5a-predctrl.s
+++ b/llvm/test/MC/AArch64/armv8.5a-predres.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predctrl < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predres < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-predctrl < %s 2>&1 | FileCheck %s --check-prefix=NOPREDCTRL
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-predres < %s 2>&1 | FileCheck %s --check-prefix=NOPREDCTRL
cfp rctx, x0
dvp rctx, x1
@@ -10,9 +10,9 @@ cpp rctx, x2
// CHECK: dvp rctx, x1 // encoding: [0xa1,0x73,0x0b,0xd5]
// CHECK: cpp rctx, x2 // encoding: [0xe2,0x73,0x0b,0xd5]
-// NOPREDCTRL: CFPRCTX requires predctrl
+// NOPREDCTRL: CFPRCTX requires predres
// NOPREDCTRL-NEXT: cfp
-// NOPREDCTRL: DVPRCTX requires predctrl
+// NOPREDCTRL: DVPRCTX requires predres
// NOPREDCTRL-NEXT: dvp
-// NOPREDCTRL: CPPRCTX requires predctrl
+// NOPREDCTRL: CPPRCTX requires predres
// NOPREDCTRL-NEXT: cpp
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-predctrl.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt
index ecfdeec86f1..5d4e0731c85 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-predctrl.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-predres.txt
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -triple=aarch64 -mattr=+predctrl -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+predres -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=-predctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+# RUN: llvm-mc -triple=aarch64 -mattr=-predres -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
[0x80 0x73 0x0b 0xd5]
[0xa1 0x73 0x0b 0xd5]
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