diff options
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/invalid-fp-armv8.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/invalid-neon-v8.s | 6 |
3 files changed, 11 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 2690eed45cd..6974c32d9b7 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5804,9 +5804,9 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands) { - // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON + // VRINT{Z, X} have a predicate operand in VFP, but not in NEON unsigned RegIdx = 3; - if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && + if ((Mnemonic == "vrintz" || Mnemonic == "vrintx") && (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { if (static_cast<ARMOperand &>(*Operands[3]).isToken() && @@ -6100,7 +6100,8 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Some instructions have the same mnemonic, but don't always // have a predicate. Distinguish them here and delete the // predicate if needed. - if (shouldOmitPredicateOperand(Mnemonic, Operands)) + if (PredicationCode == ARMCC::AL && + shouldOmitPredicateOperand(Mnemonic, Operands)) Operands.erase(Operands.begin() + 1); // ARM mode 'blx' need special handling, as the register operand version diff --git a/llvm/test/MC/ARM/invalid-fp-armv8.s b/llvm/test/MC/ARM/invalid-fp-armv8.s index da952cf7ed6..dca0e448d11 100644 --- a/llvm/test/MC/ARM/invalid-fp-armv8.s +++ b/llvm/test/MC/ARM/invalid-fp-armv8.s @@ -81,7 +81,7 @@ vcvtthi.f16.f64 q0, d3 vrintrlo.f32.f32 d3, q0 @ V8: error: invalid instruction vrintxcs.f32.f32 d3, d0 -@ V8: error: instruction requires: NEON +@ V8: error: invalid instruction vrinta.f64.f64 s3, q0 @ V8: error: invalid instruction diff --git a/llvm/test/MC/ARM/invalid-neon-v8.s b/llvm/test/MC/ARM/invalid-neon-v8.s index 6403904c1d3..cae1fb331cf 100644 --- a/llvm/test/MC/ARM/invalid-neon-v8.s +++ b/llvm/test/MC/ARM/invalid-neon-v8.s @@ -72,3 +72,9 @@ vmull.p64 s1, d2, d3 @ CHECK: error: operand must be a register in range [q0, q15] vmullge.p64 q0, d16, d17 @ CHECK: error: instruction 'vmull' is not predicable, but condition code specified + +// These instructions are predicable in VFP but not in NEON +vrintzeq.f32 d0, d1 +vrintxgt.f32 d0, d1 +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction |
