diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrControl.td | 5 | ||||
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 3 |
2 files changed, 1 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td index 7d610e6ca45..b9d5e803afe 100644 --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -52,11 +52,6 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { let hasSideEffects = 0 in def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), "jmp\t$dst", [], IIC_JMP_REL>; - // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious - // with JMP_1. - let hasSideEffects = 0 in - def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), - "jmpq\t$dst", [], IIC_JMP_REL>; } // Conditional Branches. diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index 1198e5a9779..2fa5a127a23 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -275,8 +275,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, } } // FIXME: These instructions aren't marked as 64-bit in any way - Is64Bit |= Rec->getName() == "JMP64pcrel32" || - Rec->getName().find("MOV64") != Name.npos || + Is64Bit |= Rec->getName().find("MOV64") != Name.npos || Rec->getName().find("PUSH64") != Name.npos || Rec->getName().find("POP64") != Name.npos; |
