diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SISchedule.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleGeneric.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsScheduleP5600.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleP9.td | 2 | ||||
| -rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.cpp | 3 |
5 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td index 0f02f5825cb..7af69cb6a46 100644 --- a/llvm/lib/Target/AMDGPU/SISchedule.td +++ b/llvm/lib/Target/AMDGPU/SISchedule.td @@ -46,7 +46,7 @@ def Write64Bit : SchedWrite; // instructions) class SISchedMachineModel : SchedMachineModel { - let CompleteModel = 1; + let CompleteModel = 0; // MicroOpBufferSize = 1 means that instructions will always be added // the ready queue when they become available. This exposes them // to the register pressure analysis. diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index c58693cccb2..4087f1ca44e 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -25,7 +25,7 @@ def MipsGenericModel : SchedMachineModel { int HighLatency = 37; list<Predicate> UnsupportedFeatures = []; - let CompleteModel = 1; + let CompleteModel = 0; let PostRAScheduler = 1; // FIXME: Remove when all errors have been fixed. diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index 9223f33f6b5..61dab4071a3 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -13,7 +13,7 @@ def MipsP5600Model : SchedMachineModel { int LoadLatency = 4; int MispredictPenalty = 8; // TODO: Estimated - let CompleteModel = 1; + let CompleteModel = 0; list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6, HasMips64, HasMips64r2, HasCnMips, diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td index dbebc75f693..6db2a7947af 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -33,7 +33,7 @@ def P9Model : SchedMachineModel { // A dispatch group is 6 instructions. let LoopMicroOpBufferSize = 60; - let CompleteModel = 1; + let CompleteModel = 0; // Do not support QPX (Quad Processing eXtension) on Power 9. let UnsupportedFeatures = [HasQPX]; diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index 5c52bdd0674..cc28cdfe8f1 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -1626,6 +1626,7 @@ void CodeGenSchedModels::checkCompleteness() { bool Complete = true; bool HadCompleteModel = false; for (const CodeGenProcModel &ProcModel : procModels()) { + const bool HasItineraries = ProcModel.hasItineraries(); if (!ProcModel.ModelDef->getValueAsBit("CompleteModel")) continue; for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) { @@ -1646,7 +1647,7 @@ void CodeGenSchedModels::checkCompleteness() { const CodeGenSchedClass &SC = getSchedClass(SCIdx); if (!SC.Writes.empty()) continue; - if (SC.ItinClassDef != nullptr && + if (HasItineraries && SC.ItinClassDef != nullptr && SC.ItinClassDef->getName() != "NoItinerary") continue; |
