diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp | 19 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll | 4 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/reloc.s | 12 |
3 files changed, 29 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp index 3467ae765f3..a4b4d256123 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp @@ -21,10 +21,7 @@ public: AMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend); protected: unsigned getRelocType(MCContext &Ctx, const MCValue &Target, - const MCFixup &Fixup, bool IsPCRel) const override { - return Fixup.getKind(); - } - + const MCFixup &Fixup, bool IsPCRel) const override; }; @@ -37,6 +34,20 @@ AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit, ELF::EM_AMDGPU, HasRelocationAddend) { } +unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx, + const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel) const { + // SCRATCH_RSRC_DWORD[01] is a special global variable that represents + // the scratch buffer. + if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD0") + return ELF::R_AMDGPU_ABS32_LO; + if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1") + return ELF::R_AMDGPU_ABS32_HI; + + llvm_unreachable("unhandled relocation type"); +} + MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend, diff --git a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll index 0a947328221..099f0639b34 100644 --- a/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll +++ b/llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll @@ -8,9 +8,9 @@ ; ALL-LABEL: {{^}}large_alloca_compute_shader: ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 -; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0, kind: FK_Data_4 +; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 -; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1, kind: FK_Data_4 +; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000 diff --git a/llvm/test/MC/AMDGPU/reloc.s b/llvm/test/MC/AMDGPU/reloc.s new file mode 100644 index 00000000000..ac7e863957a --- /dev/null +++ b/llvm/test/MC/AMDGPU/reloc.s @@ -0,0 +1,12 @@ +// RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations | FileCheck %s + +// CHECK: Relocations [ +// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0 +// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0 +// CHECK: ] + +kernel: + s_mov_b32 s0, SCRATCH_RSRC_DWORD0 + s_mov_b32 s1, SCRATCH_RSRC_DWORD1 + +.globl SCRATCH_RSRC_DWORD0 |
