diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 8 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 8 |
3 files changed, 14 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 80eca2487c6..55b1a3aa0fd 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2803,12 +2803,12 @@ multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec, defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec, VecOpNode, sched, prd, "{q}">, EVEX_CD8<64, CD8VF> , VEX_W; - defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode, - sched.Scl, f32x_info, prd>, - EVEX_CD8<32, CD8VT1>; - defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode, - sched.Scl, f64x_info, prd>, - EVEX_CD8<64, CD8VT1>, VEX_W; + defm SSZ : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode, + sched.Scl, f32x_info, prd>, + EVEX_CD8<32, CD8VT1>; + defm SDZ : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode, + sched.Scl, f64x_info, prd>, + EVEX_CD8<64, CD8VT1>, VEX_W; } defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass, diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index cfa25731c40..d073c0a5cc9 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -1007,8 +1007,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VEXPANDPSZrr, X86::VEXPANDPSZrm, TB_NO_REVERSE }, { X86::VFPCLASSPDZrr, X86::VFPCLASSPDZrm, 0 }, { X86::VFPCLASSPSZrr, X86::VFPCLASSPSZrm, 0 }, - { X86::VFPCLASSSDrr, X86::VFPCLASSSDrm, TB_NO_REVERSE }, - { X86::VFPCLASSSSrr, X86::VFPCLASSSSrm, TB_NO_REVERSE }, + { X86::VFPCLASSSDZrr, X86::VFPCLASSSDZrm, TB_NO_REVERSE }, + { X86::VFPCLASSSSZrr, X86::VFPCLASSSSZrm, TB_NO_REVERSE }, { X86::VGETEXPPDZr, X86::VGETEXPPDZm, 0 }, { X86::VGETEXPPSZr, X86::VGETEXPPSZm, 0 }, { X86::VGETMANTPDZrri, X86::VGETMANTPDZrmi, 0 }, @@ -3147,8 +3147,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VFPCLASSPSZ128rrk, X86::VFPCLASSPSZ128rmk, 0 }, { X86::VFPCLASSPSZ256rrk, X86::VFPCLASSPSZ256rmk, 0 }, { X86::VFPCLASSPSZrrk, X86::VFPCLASSPSZrmk, 0 }, - { X86::VFPCLASSSDrrk, X86::VFPCLASSSDrmk, TB_NO_REVERSE }, - { X86::VFPCLASSSSrrk, X86::VFPCLASSSSrmk, TB_NO_REVERSE }, + { X86::VFPCLASSSDZrrk, X86::VFPCLASSSDZrmk, TB_NO_REVERSE }, + { X86::VFPCLASSSSZrrk, X86::VFPCLASSSSZrmk, TB_NO_REVERSE }, // AES foldable instructions { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 }, diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 2a95f814570..189fcadbb83 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -823,8 +823,8 @@ def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. "VFPCLASSPD(Z|Z128|Z256)rr", "VFPCLASSPS(Z|Z128|Z256)rr", - "VFPCLASSSDrr", - "VFPCLASSSSrr", + "VFPCLASSSDZrr", + "VFPCLASSSSZrr", "VPBROADCASTBrr", "VPBROADCASTWrr", "VPCMPB(Z|Z128|Z256)rri", @@ -1608,7 +1608,7 @@ def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { let ResourceCycles = [1,1]; } def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", - "VFPCLASSSDrm(b?)", + "VFPCLASSSDZrm(b?)", "VPBROADCASTBYrm", "VPBROADCASTB(Z|Z256)m(b?)", "VPBROADCASTWYrm", @@ -1768,7 +1768,7 @@ def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i", "VCMPPSZ128rm(b?)i", "VCMPSDZrm", "VCMPSSZrm", - "VFPCLASSSSrm(b?)", + "VFPCLASSSSZrm(b?)", "VPCMPBZ128rmi(b?)", "VPCMPDZ128rmi(b?)", "VPCMPEQ(B|D|Q|W)Z128rm(b?)", |
