diff options
| -rw-r--r-- | llvm/utils/TableGen/SubtargetEmitter.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index 4b6988c15ac..c5ab391e2fb 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -1157,9 +1157,10 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { OS << " nullptr, nullptr, 0, 0," << " // No instruction-level machine model.\n"; if (PM.hasItineraries()) - OS << " " << PM.ItinsDef->getName() << "};\n"; + OS << " " << PM.ItinsDef->getName() << "\n"; else - OS << " nullptr}; // No Itinerary\n"; + OS << " nullptr // No Itinerary\n"; + OS << "};\n"; } } @@ -1225,7 +1226,7 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { // Emit the processor lookup data EmitProcessorLookup(OS); - OS << "#undef DBGFIELD"; + OS << "\n#undef DBGFIELD"; } void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName, @@ -1389,7 +1390,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { #endif // MCInstrInfo initialization routine. - OS << "static inline MCSubtargetInfo *create" << Target + OS << "\nstatic inline MCSubtargetInfo *create" << Target << "MCSubtargetInfoImpl(" << "const Triple &TT, StringRef CPU, StringRef FS) {\n"; OS << " return new MCSubtargetInfo(TT, CPU, FS, "; |
