diff options
| -rw-r--r-- | clang/lib/Basic/Targets/RISCV.cpp | 4 | ||||
| -rw-r--r-- | clang/test/CodeGen/riscv-inline-asm.c | 6 |
2 files changed, 10 insertions, 0 deletions
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index a634ba69f3c..d1166d90df4 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -75,6 +75,10 @@ bool RISCVTargetInfo::validateAsmConstraint( // A floating-point register. Info.setAllowsRegister(); return true; + case 'A': + // An address that is held in a general-purpose register. + Info.setAllowsMemory(); + return true; } } diff --git a/clang/test/CodeGen/riscv-inline-asm.c b/clang/test/CodeGen/riscv-inline-asm.c index f79527337bd..2c92d15ca90 100644 --- a/clang/test/CodeGen/riscv-inline-asm.c +++ b/clang/test/CodeGen/riscv-inline-asm.c @@ -38,3 +38,9 @@ void test_f() { // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]]) asm volatile ("" :: "f"(d)); } + +void test_A(int *p) { +// CHECK-LABEL: define void @test_A(i32* %p) +// CHECK: call void asm sideeffect "", "*A"(i32* %p) + asm volatile("" :: "A"(*p)); +} |
