diff options
| -rw-r--r-- | llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td | 15 | ||||
| -rw-r--r-- | llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp | 2 |
2 files changed, 12 insertions, 5 deletions
diff --git a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td index b3d202bf26f..6e0806a3a9d 100644 --- a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -25,13 +25,20 @@ include "../SparcRegisterInfo.td" // def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, - G1, G2, G3, G4, G5, G6, G7, + G1, O0, O1, O2, O3, O4, O5, O7, - // Non-allocatable regs - O6, I6, I7, G0]> { + // Non-allocatable regs: + G2, G3, G4, // FIXME: OK for use only in + // applications, not libraries. + O6, // stack ptr + I6, // frame ptr + I7, // return address + G0, // constant zero + G5, G6, G7 // reserved for kernel + ]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { - return end()-4; // Don't allocate special registers + return end()-10; // Don't allocate special registers } }]; } diff --git a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp index a6b69d62633..604f683499f 100644 --- a/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp +++ b/llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp @@ -31,7 +31,7 @@ namespace { /// SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL) - : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8), + : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8, 4, 4, 4, 4), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) { } |
