diff options
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 33 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86Operand.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 44 |
3 files changed, 78 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 576629fce89..e8e4b839d3b 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -2712,6 +2712,39 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { "should be distinct"); break; } + case X86::V4FMADDPSrm: + case X86::V4FMADDPSrmk: + case X86::V4FMADDPSrmkz: + case X86::V4FMADDSSrm: + case X86::V4FMADDSSrmk: + case X86::V4FMADDSSrmkz: + case X86::V4FNMADDPSrm: + case X86::V4FNMADDPSrmk: + case X86::V4FNMADDPSrmkz: + case X86::V4FNMADDSSrm: + case X86::V4FNMADDSSrmk: + case X86::V4FNMADDSSrmkz: + case X86::VP4DPWSSDSrm: + case X86::VP4DPWSSDSrmk: + case X86::VP4DPWSSDSrmkz: + case X86::VP4DPWSSDrm: + case X86::VP4DPWSSDrmk: + case X86::VP4DPWSSDrmkz: { + unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - + X86::AddrNumOperands - 1).getReg(); + unsigned Src2Enc = MRI->getEncodingValue(Src2); + if (Src2Enc % 4 != 0) { + StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2); + unsigned GroupStart = (Src2Enc / 4) * 4; + unsigned GroupEnd = GroupStart + 3; + return Warning(Ops[Ops.size()-2]->getStartLoc(), + "source register implicitly denotes '" + + RegName.take_front(3) + Twine(GroupStart) + "' to '" + + RegName.take_front(3) + Twine(GroupEnd) + + "' source group"); + } + break; + } } return false; diff --git a/llvm/lib/Target/X86/AsmParser/X86Operand.h b/llvm/lib/Target/X86/AsmParser/X86Operand.h index 2493e8321c3..906471212a3 100644 --- a/llvm/lib/Target/X86/AsmParser/X86Operand.h +++ b/llvm/lib/Target/X86/AsmParser/X86Operand.h @@ -29,7 +29,7 @@ namespace llvm { /// X86Operand - Instances of this class represent a parsed X86 machine /// instruction. -struct X86Operand : public MCParsedAsmOperand { +struct X86Operand final : public MCParsedAsmOperand { enum KindTy { Token, Register, Immediate, Memory, Prefix } Kind; SMLoc StartLoc, EndLoc; diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index cf1a5a20c0b..3e3e57c5bdb 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -11296,3 +11296,47 @@ defm VGF2P8AFFINEINVQB : GF2P8AFFINE_avx512_common<0xCF, "vgf2p8affineinvqb", defm VGF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb", X86GF2P8affineqb, SchedWriteVecIMul>, EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; + + +//===----------------------------------------------------------------------===// +// AVX5124FMAPS +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedSingle in { +defm V4FMADDPSrm : AVX512_maskable_in_asm<0x9A, MRMSrcMem, v16f32_info, + (outs VR512:$dst), (ins VR512:$src1, f128mem:$src2), + "v4fmaddps", "$src2, $src1", "$src1, $src2", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>; + +defm V4FNMADDPSrm : AVX512_maskable_in_asm<0xAA, MRMSrcMem, v16f32_info, + (outs VR512:$dst), (ins VR512:$src1, f128mem:$src2), + "v4fnmaddps", "$src2, $src1", "$src1, $src2", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>; + +defm V4FMADDSSrm : AVX512_maskable_in_asm<0x9B, MRMSrcMem, f32x_info, + (outs VR128X:$dst), (ins VR128X:$src1, f128mem:$src2), + "v4fmaddss", "$src2, $src1", "$src1, $src2", + []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>; + +defm V4FNMADDSSrm : AVX512_maskable_in_asm<0xAB, MRMSrcMem, f32x_info, + (outs VR128X:$dst), (ins VR128X:$src1, f128mem:$src2), + "v4fnmaddss", "$src2, $src1", "$src1, $src2", + []>, EVEX_V128, EVEX_4V, T8XD, EVEX_CD8<32, CD8VF>; +} + +//===----------------------------------------------------------------------===// +// AVX5124VNNIW +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, ExeDomain = SSEPackedInt in { +defm VP4DPWSSDrm : AVX512_maskable_in_asm<0x52, MRMSrcMem, v16i32_info, + (outs VR512:$dst), (ins VR512:$src1, f128mem:$src2), + "vp4dpwssd", "$src2, $src1", "$src1, $src2", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>; + +defm VP4DPWSSDSrm : AVX512_maskable_in_asm<0x53, MRMSrcMem, v16i32_info, + (outs VR512:$dst), (ins VR512:$src1, f128mem:$src2), + "vp4dpwssds", "$src2, $src1", "$src1, $src2", + []>, EVEX_V512, EVEX_4V, T8XD, EVEX_CD8<32, CD8VQ>; +} + |
