diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr3DNow.td | 133 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFormats.td | 52 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 383 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 45 |
4 files changed, 226 insertions, 387 deletions
diff --git a/llvm/lib/Target/X86/X86Instr3DNow.td b/llvm/lib/Target/X86/X86Instr3DNow.td index 065383f67a4..5ffe95e3be3 100644 --- a/llvm/lib/Target/X86/X86Instr3DNow.td +++ b/llvm/lib/Target/X86/X86Instr3DNow.td @@ -12,106 +12,72 @@ // //===----------------------------------------------------------------------===// -let Sched = WriteFAdd in { -def I3DNOW_FALU_ITINS : OpndItins< - IIC_3DNOW_FALU_RR, IIC_3DNOW_FALU_RM ->; +class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat> + : I<o, F, outs, ins, asm, pat>, Requires<[Has3DNow]> { } -let Sched = WriteCvtF2I in { -def I3DNOW_FCVT_F2I_ITINS : OpndItins< - IIC_3DNOW_FCVT_F2I_RR, IIC_3DNOW_FCVT_F2I_RM ->; -} - -let Sched = WriteCvtI2F in { -def I3DNOW_FCVT_I2F_ITINS : OpndItins< - IIC_3DNOW_FCVT_I2F_RR, IIC_3DNOW_FCVT_I2F_RM ->; -} - -let Sched = WriteVecIMul in { -def I3DNOW_MISC_FUNC_ITINS : OpndItins< - IIC_3DNOW_MISC_FUNC_REG, IIC_3DNOW_MISC_FUNC_MEM ->; -} - -let Sched = WriteShuffle in { -def I3DNOW_PSHUF_ITINS : OpndItins< - IIC_MMX_PSHUF, IIC_MMX_PSHUF ->; -} - -class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat, - InstrItinClass itin> - : I<o, F, outs, ins, asm, pat, itin>, Requires<[Has3DNow]> { -} - -class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat, - InstrItinClass itin> +class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> : I3DNow<o, F, (outs VR64:$dst), ins, - !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat, itin>, - ThreeDNow { + !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>, ThreeDNow { let Constraints = "$src1 = $dst"; } -class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat, - InstrItinClass itin> +class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> : I3DNow<o, F, (outs VR64:$dst), ins, - !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat, itin>, - ThreeDNow; + !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, ThreeDNow; -multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, OpndItins itins, - bit Commutable = 0, string Ver = ""> { +multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, + X86FoldableSchedWrite sched, bit Commutable = 0, + string Ver = ""> { let isCommutable = Commutable in def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, [(set VR64:$dst, (!cast<Intrinsic>( - !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))], - itins.rr>, Sched<[itins.Sched]>; + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>, + Sched<[sched]>; def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, [(set VR64:$dst, (!cast<Intrinsic>( !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, - (bitconvert (load_mmx addr:$src2))))], itins.rm>, - Sched<[itins.Sched.Folded, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; } -multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, OpndItins itins, - string Ver = ""> { +multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, + X86FoldableSchedWrite sched, string Ver = ""> { def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn, [(set VR64:$dst, (!cast<Intrinsic>( - !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))], itins.rr>, - Sched<[itins.Sched]>; + !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>, + Sched<[sched]>; def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn, [(set VR64:$dst, (!cast<Intrinsic>( !strconcat("int_x86_3dnow", Ver, "_", Mn)) - (bitconvert (load_mmx addr:$src))))], itins.rm>, - Sched<[itins.Sched.Folded, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src))))]>, + Sched<[sched.Folded, ReadAfterLd]>; } -defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", I3DNOW_MISC_FUNC_ITINS, 1>; -defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", I3DNOW_FCVT_F2I_ITINS>; -defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", I3DNOW_FALU_ITINS>; -defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", I3DNOW_FALU_ITINS, 1>; -defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", I3DNOW_FALU_ITINS, 1>; -defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", I3DNOW_FALU_ITINS>; -defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", I3DNOW_FALU_ITINS>; -defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", I3DNOW_FALU_ITINS>; -defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", I3DNOW_FALU_ITINS>; -defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", I3DNOW_FALU_ITINS, 1>; -defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", I3DNOW_FALU_ITINS>; -defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", I3DNOW_FALU_ITINS>; -defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", I3DNOW_FALU_ITINS>; -defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", I3DNOW_FALU_ITINS>; -defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", I3DNOW_FALU_ITINS>; -defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", I3DNOW_FALU_ITINS, 1>; -defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", I3DNOW_FALU_ITINS, 1>; -defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", I3DNOW_FCVT_I2F_ITINS>; -defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", I3DNOW_MISC_FUNC_ITINS, 1>; +defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", WriteVecIMul, 1>; +defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtF2I>; +defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>; +defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>; +defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>; +defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>; +defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>; +defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>; +defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>; +defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>; +defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>; +defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>; +defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>; +defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>; +defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>; +defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>; +defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>; +defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2F>; +defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", WriteVecIMul, 1>; // FIXME: Is there a better scheduler class for EMMS/FEMMS? let SchedRW = [WriteMicrocoded] in def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", - [(int_x86_mmx_femms)], IIC_MMX_EMMS>, TB; + [(int_x86_mmx_femms)]>, TB; // PREFETCHWT1 is supported we want to use it for everything but T0. def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{ @@ -127,21 +93,20 @@ let SchedRW = [WriteLoad] in { let Predicates = [Has3DNow, NoSSEPrefetch] in def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), "prefetch\t$addr", - [(prefetch addr:$addr, imm, imm, (i32 1))], - IIC_SSE_PREFETCH>, TB; + [(prefetch addr:$addr, imm, imm, (i32 1))]>, TB; def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", - [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))], - IIC_SSE_PREFETCH>, TB, Requires<[HasPrefetchW]>; + [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>, + TB, Requires<[HasPrefetchW]>; def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr", - [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))], - IIC_SSE_PREFETCH>, TB, Requires<[HasPREFETCHWT1]>; + [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))]>, + TB, Requires<[HasPREFETCHWT1]>; } // "3DNowA" instructions -defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", I3DNOW_FCVT_F2I_ITINS, "a">; -defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", I3DNOW_FCVT_I2F_ITINS, "a">; -defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", I3DNOW_FALU_ITINS, 0, "a">; -defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", I3DNOW_FALU_ITINS, 0, "a">; -defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", I3DNOW_PSHUF_ITINS, "a">; +defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtF2I, "a">; +defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2F, "a">; +defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">; +defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">; +defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", WriteShuffle, "a">; diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td index dff6d1e9ae2..f271b6869d5 100644 --- a/llvm/lib/Target/X86/X86InstrFormats.td +++ b/llvm/lib/Target/X86/X86InstrFormats.td @@ -528,8 +528,8 @@ class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, // MMXPI - SSE 1 & 2 packed instructions with MMX operands class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, - InstrItinClass itin, Domain d> - : I<o, F, outs, ins, asm, pattern, itin, d> { + Domain d> + : I<o, F, outs, ins, asm, pattern, NoItinerary, d> { let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2], [HasSSE1]); } @@ -638,11 +638,11 @@ class S2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>; class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>; + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>; class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE2]>; + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>; // SSE3 Instruction Templates: // @@ -684,12 +684,12 @@ class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD, Requires<[UseSSSE3]>; class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PS, + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern, NoItinerary, SSEPackedInt>, T8PS, Requires<[HasSSSE3]>; class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPS, + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern, NoItinerary, SSEPackedInt>, TAPS, Requires<[HasSSSE3]>; // SSE4.1 Instruction Templates: @@ -963,26 +963,26 @@ class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX]>; class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>; + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,Not64BitMode]>; class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>; + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,In64BitMode]>; class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>; + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, PS, REX_W, Requires<[HasMMX]>; class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>; + list<dag> pattern> + : I<o, F, outs, ins, asm, pattern>, PD, Requires<[HasMMX]>; class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX]>; class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>; + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>; class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>; + list<dag> pattern> + : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>; diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index a95fdd4c800..a45bd830eda 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -20,77 +20,6 @@ // MMX Multiclasses //===----------------------------------------------------------------------===// -let Sched = WriteVecALU in { -def MMX_INTALU_ITINS : OpndItins< - IIC_MMX_ALU_RR, IIC_MMX_ALU_RM ->; - -def MMX_INTALUQ_ITINS : OpndItins< - IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM ->; - -def MMX_PHADDSUBW : OpndItins< - IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM ->; - -def MMX_PHADDSUBD : OpndItins< - IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM ->; -} - -let Sched = WriteVecLogic in -def MMX_INTALU_ITINS_VECLOGICSCHED : OpndItins< - IIC_MMX_ALU_RR, IIC_MMX_ALU_RM ->; - -let Sched = WriteVecIMul in -def MMX_PMUL_ITINS : OpndItins< - IIC_MMX_PMUL, IIC_MMX_PMUL ->; - -let Sched = WriteVecIMul in { -def MMX_PSADBW_ITINS : OpndItins< - IIC_MMX_PSADBW, IIC_MMX_PSADBW ->; - -def MMX_MISC_FUNC_ITINS : OpndItins< - IIC_MMX_MISC_FUNC_REG, IIC_MMX_MISC_FUNC_MEM ->; -} - -def MMX_SHIFT_ITINS : ShiftOpndItins< - IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI ->; - -let Sched = WriteShuffle in { -def MMX_UNPCK_H_ITINS : OpndItins< - IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM ->; - -def MMX_UNPCK_L_ITINS : OpndItins< - IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L ->; - -def MMX_PCK_ITINS : OpndItins< - IIC_MMX_PCK_RR, IIC_MMX_PCK_RM ->; -} // Sched - -let Sched = WriteVarShuffle in -def MMX_PSHUF_ITINS : OpndItins< - IIC_MMX_PSHUF, IIC_MMX_PSHUF ->; - -let Sched = WriteCvtF2I in { -def MMX_CVT_PD_ITINS : OpndItins< - IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM ->; - -def MMX_CVT_PS_ITINS : OpndItins< - IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM ->; -} - // Alias instruction that maps zero vector to pxor mmx. // This is expanded by ExpandPostRAPseudos to an pxor. // We set canFoldAsLoad because this can be converted to a constant-pool @@ -104,78 +33,78 @@ let Constraints = "$src1 = $dst" in { // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, - OpndItins itins, bit Commutable = 0, + X86FoldableSchedWrite sched, bit Commutable = 0, X86MemOperand OType = i64mem> { def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), - [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>, - Sched<[itins.Sched]> { + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>, + Sched<[sched]> { let isCommutable = Commutable; } def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, OType:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, - (bitconvert (load_mmx addr:$src2))))], - itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; } multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, string OpcodeStr, Intrinsic IntId, - Intrinsic IntId2, ShiftOpndItins itins> { + Intrinsic IntId2, X86FoldableSchedWrite sched> { def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), - [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>, - Sched<[WriteVecShift]>; + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>, + Sched<[sched]>; def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, - (bitconvert (load_mmx addr:$src2))))], - itins.rm>, Sched<[WriteVecShiftLd, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32u8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), - [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))], itins.ri>, - Sched<[WriteVecShift]>; + [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))]>, + Sched<[sched]>; } } /// Unary MMX instructions requiring SSSE3. multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr, - Intrinsic IntId64, OpndItins itins> { + Intrinsic IntId64, X86FoldableSchedWrite sched> { def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>, - Sched<[itins.Sched]>; + [(set VR64:$dst, (IntId64 VR64:$src))]>, + Sched<[sched]>; def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(set VR64:$dst, - (IntId64 (bitconvert (load_mmx addr:$src))))], - itins.rm>, Sched<[itins.Sched.Folded]>; + (IntId64 (bitconvert (load_mmx addr:$src))))]>, + Sched<[sched.Folded]>; } /// Binary MMX instructions requiring SSSE3. let ImmT = NoImm, Constraints = "$src1 = $dst" in { multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr, - Intrinsic IntId64, OpndItins itins, + Intrinsic IntId64, X86FoldableSchedWrite sched, bit Commutable = 0> { let isCommutable = Commutable in def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), - [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>, - Sched<[itins.Sched]>; + [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>, + Sched<[sched]>; def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId64 VR64:$src1, - (bitconvert (load_mmx addr:$src2))))], itins.rm>, - Sched<[itins.Sched.Folded, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src2))))]>, + Sched<[sched.Folded, ReadAfterLd]>; } } @@ -184,38 +113,38 @@ multiclass ssse3_palign_mm<string asm, Intrinsic IntId> { def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2, u8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), - [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))], - IIC_MMX_PSHUF>, Sched<[WriteShuffle]>; + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>, + Sched<[WriteShuffle]>; def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2, u8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR64:$dst, (IntId VR64:$src1, - (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))], - IIC_MMX_PSHUF>, Sched<[WriteShuffleLd, ReadAfterLd]>; + (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>, + Sched<[WriteShuffleLd, ReadAfterLd]>; } multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, - string asm, OpndItins itins, Domain d> { + string asm, X86FoldableSchedWrite sched, Domain d> { def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, - [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>, - Sched<[itins.Sched]>; + [(set DstRC:$dst, (Int SrcRC:$src))], d>, + Sched<[sched]>; def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, - [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>, - Sched<[itins.Sched.Folded]>; + [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>, + Sched<[sched.Folded]>; } multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, - PatFrag ld_frag, string asm, OpndItins itins, Domain d> { + PatFrag ld_frag, string asm, Domain d> { def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2), asm, - [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], - itins.rr, d>, Sched<[WriteCvtI2F]>; + [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>, + Sched<[WriteCvtI2F]>; def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins DstRC:$src1, x86memop:$src2), asm, - [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], - itins.rm, d>, Sched<[WriteCvtI2FLd]>; + [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>, + Sched<[WriteCvtI2FLd]>; } //===----------------------------------------------------------------------===// @@ -224,8 +153,7 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, // FIXME: Is there a better scheduler class for EMMS/FEMMS? let SchedRW = [WriteMicrocoded] in -def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", - [(int_x86_mmx_emms)], IIC_MMX_EMMS>; +def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>; //===----------------------------------------------------------------------===// // MMX Scalar Instructions @@ -235,13 +163,13 @@ def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", [(set VR64:$dst, - (x86mmx (scalar_to_vector GR32:$src)))], - IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; + (x86mmx (scalar_to_vector GR32:$src)))]>, + Sched<[WriteMove]>; def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), "movd\t{$src, $dst|$dst, $src}", [(set VR64:$dst, - (x86mmx (scalar_to_vector (loadi32 addr:$src))))], - IIC_MMX_MOV_MM_RM>, Sched<[WriteLoad]>; + (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>, + Sched<[WriteLoad]>; let Predicates = [HasMMX] in { let AddedComplexity = 15 in @@ -257,26 +185,25 @@ let Predicates = [HasMMX] in { let mayStore = 1 in def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), - "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>, + "movd\t{$src, $dst|$dst, $src}", []>, Sched<[WriteStore]>; def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), "movd\t{$src, $dst|$dst, $src}", [(set GR32:$dst, - (MMX_X86movd2w (x86mmx VR64:$src)))], - IIC_MMX_MOV_REG_MM>, Sched<[WriteMove]>, - FoldGenData<"MMX_MOVD64rr">; + (MMX_X86movd2w (x86mmx VR64:$src)))]>, + Sched<[WriteMove]>, FoldGenData<"MMX_MOVD64rr">; let isBitcast = 1 in def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), "movq\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, (bitconvert GR64:$src))], - IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; + [(set VR64:$dst, (bitconvert GR64:$src))]>, + Sched<[WriteMove]>; let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", - [], IIC_MMX_MOVQ_RM>, Sched<[WriteLoad]>; + []>, Sched<[WriteLoad]>; // These are 64 bit moves, but since the OS X assembler doesn't // recognize a register-register movq, we write them as @@ -285,38 +212,34 @@ let SchedRW = [WriteMove], isBitcast = 1 in { def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR64:$src), "movq\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, - (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>; + [(set GR64:$dst, (bitconvert VR64:$src))]>; let hasSideEffects = 0 in def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), - "movq\t{$src, $dst|$dst, $src}", [], - IIC_MMX_MOVQ_RR>; + "movq\t{$src, $dst|$dst, $src}", []>; let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src), - "movq\t{$src, $dst|$dst, $src}", [], - IIC_MMX_MOVQ_RR>, FoldGenData<"MMX_MOVQ64rr">; + "movq\t{$src, $dst|$dst, $src}", []>, + FoldGenData<"MMX_MOVQ64rr">; } } // SchedRW let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), - "movq\t{$src, $dst|$dst, $src}", - [], IIC_MMX_MOV_REG_MM>, Sched<[WriteStore]>; + "movq\t{$src, $dst|$dst, $src}", []>, + Sched<[WriteStore]>; let SchedRW = [WriteLoad] in { let canFoldAsLoad = 1 in def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, (load_mmx addr:$src))], - IIC_MMX_MOVQ_RM>; + [(set VR64:$dst, (load_mmx addr:$src))]>; } // SchedRW let SchedRW = [WriteStore] in def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movq\t{$src, $dst|$dst, $src}", - [(store (x86mmx VR64:$src), addr:$dst)], - IIC_MMX_MOVQ_RM>; + [(store (x86mmx VR64:$src), addr:$dst)]>; let SchedRW = [WriteVecMove] in { def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), @@ -324,33 +247,31 @@ def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), [(set VR64:$dst, (x86mmx (bitconvert (i64 (extractelt (v2i64 VR128:$src), - (iPTR 0))))))], - IIC_MMX_MOVQ_RR>; + (iPTR 0))))))]>; def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector - (i64 (bitconvert (x86mmx VR64:$src))))))], - IIC_MMX_MOVQ_RR>; + (i64 (bitconvert (x86mmx VR64:$src))))))]>; let isCodeGenOnly = 1, hasSideEffects = 1 in { def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", - [], IIC_MMX_MOVQ_RR>; + []>; def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", - [], IIC_MMX_MOVQ_RR>; + []>; } } // SchedRW let Predicates = [HasSSE1] in def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), "movntq\t{$src, $dst|$dst, $src}", - [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)], - IIC_MMX_MOVQ_RM>, Sched<[WriteStore]>; + [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>, + Sched<[WriteStore]>; let Predicates = [HasMMX] in { let AddedComplexity = 15 in @@ -364,240 +285,240 @@ let Predicates = [HasMMX] in { // Arithmetic Instructions defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d, - MMX_INTALU_ITINS>; + WriteVecALU>; // -- Addition defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; let Predicates = [HasSSE2] in defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, - MMX_INTALUQ_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, - MMX_INTALU_ITINS, 1>; + WriteVecALU, 1>; defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w, - MMX_PHADDSUBW>; + WriteVecALU>; defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d, - MMX_PHADDSUBD>; + WriteVecALU>; defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw, - MMX_PHADDSUBW>; + WriteVecALU>; // -- Subtraction defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d, - MMX_INTALU_ITINS>; + WriteVecALU>; let Predicates = [HasSSE2] in defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q, - MMX_INTALUQ_ITINS>; + WriteVecALU>; defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w, - MMX_PHADDSUBW>; + WriteVecALU>; defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d, - MMX_PHADDSUBD>; + WriteVecALU>; defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw, - MMX_PHADDSUBW>; + WriteVecALU>; // -- Multiplication defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, - MMX_PMUL_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, - MMX_PMUL_ITINS, 1>; + WriteVecIMul, 1>; let Predicates = [HasSSE1] in defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, - MMX_PMUL_ITINS, 1>; + WriteVecIMul, 1>; let Predicates = [HasSSE2] in defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, - MMX_PMUL_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", int_x86_ssse3_pmul_hr_sw, - MMX_PMUL_ITINS, 1>; + WriteVecIMul, 1>; // -- Miscellanea defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, - MMX_PMUL_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", - int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>; + int_x86_ssse3_pmadd_ub_sw, WriteVecIMul>; let Predicates = [HasSSE1] in { defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, - MMX_MISC_FUNC_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, - MMX_MISC_FUNC_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, - MMX_MISC_FUNC_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, - MMX_MISC_FUNC_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, - MMX_MISC_FUNC_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, - MMX_MISC_FUNC_ITINS, 1>; + WriteVecIMul, 1>; defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, - MMX_PSADBW_ITINS, 1>; + WriteVecIMul, 1>; } defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, - MMX_MISC_FUNC_ITINS>; + WriteVecIMul>; defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w, - MMX_MISC_FUNC_ITINS>; + WriteVecIMul>; defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d, - MMX_MISC_FUNC_ITINS>; + WriteVecIMul>; let Constraints = "$src1 = $dst" in defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; // Logical Instructions defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, - MMX_INTALU_ITINS_VECLOGICSCHED, 1>; + WriteVecLogic, 1>; defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, - MMX_INTALU_ITINS_VECLOGICSCHED, 1>; + WriteVecLogic, 1>; defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, - MMX_INTALU_ITINS_VECLOGICSCHED, 1>; + WriteVecLogic, 1>; defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, - MMX_INTALU_ITINS_VECLOGICSCHED>; + WriteVecLogic>; // Shift Instructions defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_mmx_psll_w, int_x86_mmx_pslli_w, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_mmx_psll_d, int_x86_mmx_pslli_d, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_mmx_psll_q, int_x86_mmx_pslli_q, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_mmx_psra_w, int_x86_mmx_psrai_w, - MMX_SHIFT_ITINS>; + WriteVecShift>; defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_mmx_psra_d, int_x86_mmx_psrai_d, - MMX_SHIFT_ITINS>; + WriteVecShift>; // Comparison Instructions defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w, - MMX_INTALU_ITINS>; + WriteVecALU>; defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d, - MMX_INTALU_ITINS>; + WriteVecALU>; // -- Unpack Instructions defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", int_x86_mmx_punpckhbw, - MMX_UNPCK_H_ITINS>; + WriteShuffle>; defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", int_x86_mmx_punpckhwd, - MMX_UNPCK_H_ITINS>; + WriteShuffle>; defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", int_x86_mmx_punpckhdq, - MMX_UNPCK_H_ITINS>; + WriteShuffle>; defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", int_x86_mmx_punpcklbw, - MMX_UNPCK_L_ITINS, + WriteShuffle, 0, i32mem>; defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", int_x86_mmx_punpcklwd, - MMX_UNPCK_L_ITINS, + WriteShuffle, 0, i32mem>; defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", int_x86_mmx_punpckldq, - MMX_UNPCK_L_ITINS, + WriteShuffle, 0, i32mem>; // -- Pack Instructions defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb, - MMX_PCK_ITINS>; + WriteShuffle>; defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw, - MMX_PCK_ITINS>; + WriteShuffle>; defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb, - MMX_PCK_ITINS>; + WriteShuffle>; // -- Shuffle Instructions defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b, - MMX_PSHUF_ITINS>; + WriteVarShuffle>; def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2), "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR64:$dst, - (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))], - IIC_MMX_PSHUF>, Sched<[WriteShuffle]>; + (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>, + Sched<[WriteShuffle]>; def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2), "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR64:$dst, (int_x86_sse_pshuf_w (load_mmx addr:$src1), - imm:$src2))], - IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>; + imm:$src2))]>, + Sched<[WriteShuffleLd]>; // -- Conversion Instructions defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", - MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; + WriteCvtF2I, SSEPackedSingle>, PS; defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", - MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; + WriteCvtF2I, SSEPackedDouble>, PD; defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", - MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; + WriteCvtF2I, SSEPackedSingle>, PS; defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", - MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; + WriteCvtF2I, SSEPackedDouble>, PD; defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", - MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; + WriteCvtI2F, SSEPackedDouble>, PD; let Constraints = "$src1 = $dst" in { defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, int_x86_sse_cvtpi2ps, i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", - MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; + SSEPackedSingle>, PS; } // Extract / Insert @@ -606,8 +527,8 @@ def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, - imm:$src2))], - IIC_MMX_PEXTR>, Sched<[WriteShuffle]>; + imm:$src2))]>, + Sched<[WriteShuffle]>; let Constraints = "$src1 = $dst" in { let Predicates = [HasSSE1] in { def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg, @@ -615,8 +536,8 @@ let Predicates = [HasSSE1] in { (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, - GR32orGR64:$src2, imm:$src3))], - IIC_MMX_PINSRW>, Sched<[WriteShuffle]>; + GR32orGR64:$src2, imm:$src3))]>, + Sched<[WriteShuffle]>; def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem, (outs VR64:$dst), @@ -624,8 +545,8 @@ let Predicates = [HasSSE1] in { "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, (i32 (anyext (loadi16 addr:$src2))), - imm:$src3))], - IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>; + imm:$src3))]>, + Sched<[WriteShuffleLd, ReadAfterLd]>; } } @@ -635,8 +556,8 @@ def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR64:$src), "pmovmskb\t{$src, $dst|$dst, $src}", [(set GR32orGR64:$dst, - (int_x86_mmx_pmovmskb VR64:$src))], - IIC_MMX_MOVMSK>, Sched<[WriteMMXMOVMSK]>; + (int_x86_mmx_pmovmskb VR64:$src))]>, + Sched<[WriteMMXMOVMSK]>; // Low word of XMM to MMX. def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, @@ -653,13 +574,11 @@ let SchedRW = [WriteShuffle] in { let Uses = [EDI], Predicates = [HasSSE1,Not64BitMode] in def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), "maskmovq\t{$mask, $src|$src, $mask}", - [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)], - IIC_MMX_MASKMOV>; + [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>; let Uses = [RDI], Predicates = [HasSSE1,In64BitMode] in def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), "maskmovq\t{$mask, $src|$src, $mask}", - [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)], - IIC_MMX_MASKMOV>; + [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>; } // 64-bit bit convert. diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index 5ffa6659b98..410f32166e5 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -437,51 +437,6 @@ def IIC_SSE_CVT_SD2SI_RR : InstrItinClass; def IIC_AVX_ZERO : InstrItinClass; -// MMX -def IIC_MMX_MOV_MM_RM : InstrItinClass; -def IIC_MMX_MOV_REG_MM : InstrItinClass; -def IIC_MMX_MOVQ_RM : InstrItinClass; -def IIC_MMX_MOVQ_RR : InstrItinClass; - -def IIC_MMX_ALU_RM : InstrItinClass; -def IIC_MMX_ALU_RR : InstrItinClass; -def IIC_MMX_ALUQ_RM : InstrItinClass; -def IIC_MMX_ALUQ_RR : InstrItinClass; -def IIC_MMX_PHADDSUBW_RM : InstrItinClass; -def IIC_MMX_PHADDSUBW_RR : InstrItinClass; -def IIC_MMX_PHADDSUBD_RM : InstrItinClass; -def IIC_MMX_PHADDSUBD_RR : InstrItinClass; -def IIC_MMX_PMUL : InstrItinClass; -def IIC_MMX_MISC_FUNC_MEM : InstrItinClass; -def IIC_MMX_MISC_FUNC_REG : InstrItinClass; -def IIC_MMX_PSADBW : InstrItinClass; -def IIC_MMX_SHIFT_RI : InstrItinClass; -def IIC_MMX_SHIFT_RM : InstrItinClass; -def IIC_MMX_SHIFT_RR : InstrItinClass; -def IIC_MMX_UNPCK_H_RM : InstrItinClass; -def IIC_MMX_UNPCK_H_RR : InstrItinClass; -def IIC_MMX_UNPCK_L : InstrItinClass; -def IIC_MMX_PCK_RM : InstrItinClass; -def IIC_MMX_PCK_RR : InstrItinClass; -def IIC_MMX_PSHUF : InstrItinClass; -def IIC_MMX_PEXTR : InstrItinClass; -def IIC_MMX_PINSRW : InstrItinClass; -def IIC_MMX_MASKMOV : InstrItinClass; -def IIC_MMX_MOVMSK : InstrItinClass; -def IIC_MMX_CVT_PD_RR : InstrItinClass; -def IIC_MMX_CVT_PD_RM : InstrItinClass; -def IIC_MMX_CVT_PS_RR : InstrItinClass; -def IIC_MMX_CVT_PS_RM : InstrItinClass; - -def IIC_3DNOW_FALU_RM : InstrItinClass; -def IIC_3DNOW_FALU_RR : InstrItinClass; -def IIC_3DNOW_FCVT_F2I_RM : InstrItinClass; -def IIC_3DNOW_FCVT_F2I_RR : InstrItinClass; -def IIC_3DNOW_FCVT_I2F_RM : InstrItinClass; -def IIC_3DNOW_FCVT_I2F_RR : InstrItinClass; -def IIC_3DNOW_MISC_FUNC_REG : InstrItinClass; -def IIC_3DNOW_MISC_FUNC_MEM : InstrItinClass; - def IIC_CMPX_LOCK : InstrItinClass; def IIC_CMPX_LOCK_8 : InstrItinClass; def IIC_CMPX_LOCK_8B : InstrItinClass; |
