diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/vec_shift5.ll | 4 |
2 files changed, 12 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 60eefbc677d..e360177687b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -39699,14 +39699,22 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG, getTargetConstantBitsFromNode(N0, NumBitsPerElt, UndefElts, EltBits)) { assert(EltBits.size() == VT.getVectorNumElements() && "Unexpected shift value type"); - for (APInt &Elt : EltBits) { - if (X86ISD::VSHLI == Opcode) + // Undef elements need to fold to 0. It's possible SimplifyDemandedBits + // created an undef input due to no input bits being demanded, but user + // still expects 0 in other bits. + for (unsigned i = 0, e = EltBits.size(); i != e; ++i) { + APInt &Elt = EltBits[i]; + if (UndefElts[i]) + Elt = 0; + else if (X86ISD::VSHLI == Opcode) Elt <<= ShiftVal; else if (X86ISD::VSRAI == Opcode) Elt.ashrInPlace(ShiftVal); else Elt.lshrInPlace(ShiftVal); } + // Reset undef elements since they were zeroed above. + UndefElts = 0; return getConstVector(EltBits, UndefElts, VT.getSimpleVT(), DAG, SDLoc(N)); } diff --git a/llvm/test/CodeGen/X86/vec_shift5.ll b/llvm/test/CodeGen/X86/vec_shift5.ll index 873de4b0834..5c84d7c748f 100644 --- a/llvm/test/CodeGen/X86/vec_shift5.ll +++ b/llvm/test/CodeGen/X86/vec_shift5.ll @@ -149,7 +149,7 @@ define <4 x i32> @test10() { define <2 x i64> @test11() { ; X32-LABEL: test11: ; X32: # %bb.0: -; X32-NEXT: movaps {{.*#+}} xmm0 = <u,u,3,0> +; X32-NEXT: movaps {{.*#+}} xmm0 = [0,0,3,0] ; X32-NEXT: retl ; ; X64-LABEL: test11: @@ -219,7 +219,7 @@ define <4 x i32> @test15() { define <2 x i64> @test16() { ; X32-LABEL: test16: ; X32: # %bb.0: -; X32-NEXT: movaps {{.*#+}} xmm0 = <u,u,248,0> +; X32-NEXT: movaps {{.*#+}} xmm0 = [0,0,248,0] ; X32-NEXT: retl ; ; X64-LABEL: test16: |
