diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/circ-load-isel.ll | 18 |
2 files changed, 20 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 734c1b41021..f22e17c296d 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -654,7 +654,7 @@ bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) { // This transformation will leave the intrinsic dead. If it remains in // the DAG, the selection code will see it again, but without the load, // and it will generate a store that is normally required for it. - CurDAG->RemoveDeadNodes(); + CurDAG->RemoveDeadNode(C); return true; } @@ -1045,6 +1045,7 @@ void HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) { void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) { if (MachineSDNode *L = LoadInstrForLoadIntrinsic(N)) { StoreInstrForLoadIntrinsic(L, N); + CurDAG->RemoveDeadNode(N); return; } SelectCode(N); diff --git a/llvm/test/CodeGen/Hexagon/circ-load-isel.ll b/llvm/test/CodeGen/Hexagon/circ-load-isel.ll new file mode 100644 index 00000000000..576fbdf53cf --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/circ-load-isel.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: = memw{{.*}}circ + +target triple = "hexagon" + +@l = external global i32, align 4 + +; Function Attrs: nounwind optsize +define void @circ2() #0 { +entry: + store i32 0, i32* @l, align 4 + %0 = tail call i8* @llvm.hexagon.circ.ldw(i8* undef, i8* undef, i32 150995968, i32 4) + unreachable +} + +declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) #1 +attributes #0 = { nounwind optsize } +attributes #1 = { argmemonly nounwind } |
