diff options
| -rw-r--r-- | llvm/test/CodeGen/AArch64/bics.ll | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/bics.ll b/llvm/test/CodeGen/AArch64/bics.ll new file mode 100644 index 00000000000..1c0c0793d36 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/bics.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s + +define i1 @andn_cmp(i32 %x, i32 %y) { +; CHECK-LABEL: andn_cmp: +; CHECK: // BB#0: +; CHECK-NEXT: bics wzr, w1, w0 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret +; + %notx = xor i32 %x, -1 + %and = and i32 %notx, %y + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +; FIXME: Recognize a disguised bics. + +define i1 @and_cmp(i32 %x, i32 %y) { +; CHECK-LABEL: and_cmp: +; CHECK: // BB#0: +; CHECK-NEXT: and w8, w0, w1 +; CHECK-NEXT: cmp w8, w1 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret +; + %and = and i32 %x, %y + %cmp = icmp eq i32 %and, %y + ret i1 %cmp +} + +define i1 @and_cmp_const(i32 %x) { +; CHECK-LABEL: and_cmp_const: +; CHECK: // BB#0: +; CHECK-NEXT: mov w8, #43 +; CHECK-NEXT: and w8, w0, w8 +; CHECK-NEXT: cmp w8, #43 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret +; + %and = and i32 %x, 43 + %cmp = icmp eq i32 %and, 43 + ret i1 %cmp +} + |
