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-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.cpp119
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.h7
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedExynosM1.td17
-rw-r--r--llvm/lib/Target/AArch64/AArch64SchedExynosM3.td13
4 files changed, 86 insertions, 70 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index e6474046534..503bda08a9c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -829,6 +829,71 @@ bool AArch64InstrInfo::isExynosResetFast(const MachineInstr &MI) const {
}
}
+bool AArch64InstrInfo::isExynosLdStExtFast(const MachineInstr &MI) const {
+ unsigned Imm;
+ AArch64_AM::ShiftExtendType Ext;
+
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+
+ // WriteLD
+ case AArch64::PRFMroW:
+ case AArch64::PRFMroX:
+
+ // WriteLDIdx
+ case AArch64::LDRBBroW:
+ case AArch64::LDRBBroX:
+ case AArch64::LDRHHroW:
+ case AArch64::LDRHHroX:
+ case AArch64::LDRSBWroW:
+ case AArch64::LDRSBWroX:
+ case AArch64::LDRSBXroW:
+ case AArch64::LDRSBXroX:
+ case AArch64::LDRSHWroW:
+ case AArch64::LDRSHWroX:
+ case AArch64::LDRSHXroW:
+ case AArch64::LDRSHXroX:
+ case AArch64::LDRSWroW:
+ case AArch64::LDRSWroX:
+ case AArch64::LDRWroW:
+ case AArch64::LDRWroX:
+ case AArch64::LDRXroW:
+ case AArch64::LDRXroX:
+
+ case AArch64::LDRBroW:
+ case AArch64::LDRBroX:
+ case AArch64::LDRDroW:
+ case AArch64::LDRDroX:
+ case AArch64::LDRHroW:
+ case AArch64::LDRHroX:
+ case AArch64::LDRSroW:
+ case AArch64::LDRSroX:
+
+ // WriteSTIdx
+ case AArch64::STRBBroW:
+ case AArch64::STRBBroX:
+ case AArch64::STRHHroW:
+ case AArch64::STRHHroX:
+ case AArch64::STRWroW:
+ case AArch64::STRWroX:
+ case AArch64::STRXroW:
+ case AArch64::STRXroX:
+
+ case AArch64::STRBroW:
+ case AArch64::STRBroX:
+ case AArch64::STRDroW:
+ case AArch64::STRDroX:
+ case AArch64::STRHroW:
+ case AArch64::STRHroX:
+ case AArch64::STRSroW:
+ case AArch64::STRSroX:
+ Imm = MI.getOperand(3).getImm();
+ Ext = AArch64_AM::getMemExtendType(Imm);
+ return (Ext == AArch64_AM::SXTX || Ext == AArch64_AM::UXTX);
+ }
+}
+
bool AArch64InstrInfo::isExynosShiftExtFast(const MachineInstr &MI) const {
unsigned Imm, Shift;
AArch64_AM::ShiftExtendType Ext;
@@ -895,60 +960,6 @@ bool AArch64InstrInfo::isExynosShiftExtFast(const MachineInstr &MI) const {
Shift = AArch64_AM::getArithShiftValue(Imm);
Ext = AArch64_AM::getArithExtendType(Imm);
return (Shift == 0 || (Shift <= 3 && Ext == AArch64_AM::UXTX));
-
- case AArch64::PRFMroW:
- case AArch64::PRFMroX:
-
- // WriteLDIdx
- case AArch64::LDRBBroW:
- case AArch64::LDRBBroX:
- case AArch64::LDRHHroW:
- case AArch64::LDRHHroX:
- case AArch64::LDRSBWroW:
- case AArch64::LDRSBWroX:
- case AArch64::LDRSBXroW:
- case AArch64::LDRSBXroX:
- case AArch64::LDRSHWroW:
- case AArch64::LDRSHWroX:
- case AArch64::LDRSHXroW:
- case AArch64::LDRSHXroX:
- case AArch64::LDRSWroW:
- case AArch64::LDRSWroX:
- case AArch64::LDRWroW:
- case AArch64::LDRWroX:
- case AArch64::LDRXroW:
- case AArch64::LDRXroX:
-
- case AArch64::LDRBroW:
- case AArch64::LDRBroX:
- case AArch64::LDRDroW:
- case AArch64::LDRDroX:
- case AArch64::LDRHroW:
- case AArch64::LDRHroX:
- case AArch64::LDRSroW:
- case AArch64::LDRSroX:
-
- // WriteSTIdx
- case AArch64::STRBBroW:
- case AArch64::STRBBroX:
- case AArch64::STRHHroW:
- case AArch64::STRHHroX:
- case AArch64::STRWroW:
- case AArch64::STRWroX:
- case AArch64::STRXroW:
- case AArch64::STRXroX:
-
- case AArch64::STRBroW:
- case AArch64::STRBroX:
- case AArch64::STRDroW:
- case AArch64::STRDroX:
- case AArch64::STRHroW:
- case AArch64::STRHroX:
- case AArch64::STRSroW:
- case AArch64::STRSroX:
- Imm = MI.getOperand(3).getImm();
- Ext = AArch64_AM::getMemExtendType(Imm);
- return (Ext == AArch64_AM::SXTX || Ext == AArch64_AM::UXTX);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 49ea9ad0fda..05721336df7 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -250,11 +250,14 @@ public:
MachineBasicBlock::iterator &It, MachineFunction &MF,
const outliner::Candidate &C) const override;
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
- /// Returns true if the instruction sets to an immediate value that can be
+ /// Returns true if the instruction sets a constant value that can be
/// executed more efficiently.
bool isExynosResetFast(const MachineInstr &MI) const;
- /// Returns true if the instruction has a shift left that can be executed
+ /// Returns true if the load or store has an extension that can be executed
/// more efficiently.
+ bool isExynosLdStExtFast(const MachineInstr &MI) const;
+ /// Returns true if the instruction has a constant shift left or extension
+ /// that can be executed more efficiently.
bool isExynosShiftExtFast(const MachineInstr &MI) const;
/// Returns true if the instruction has a shift by immediate that can be
/// executed in one cycle less.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
index c19ec45dab4..d566a13dc67 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM1.td
@@ -66,6 +66,7 @@ def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
def M1BranchLinkPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
MI->getOperand(0).getReg() != AArch64::LR}]>;
+def M1LdStExtPred : SchedPredicate<[{TII->isExynosLdStExtFast(*MI)}]>;
def M1ShiftExtPred : SchedPredicate<[{TII->isExynosShiftExtFast(*MI)}]>;
//===----------------------------------------------------------------------===//
@@ -110,10 +111,10 @@ def M1WriteLD : SchedWriteRes<[M1UnitL,
let ResourceCycles = [2, 1]; }
def M1WriteLH : SchedWriteRes<[]> { let Latency = 5;
let NumMicroOps = 0; }
-def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteL5]>,
- SchedVar<NoSchedPred, [M1WriteLC]>]>;
-def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteL5]>,
- SchedVar<NoSchedPred, [M1WriteLD]>]>;
+def M1WriteLX : SchedWriteVariant<[SchedVar<M1LdStExtPred, [M1WriteL5]>,
+ SchedVar<NoSchedPred, [M1WriteLC]>]>;
+def M1WriteLY : SchedWriteVariant<[SchedVar<M1LdStExtPred, [M1WriteL5]>,
+ SchedVar<NoSchedPred, [M1WriteLD]>]>;
def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
def M1WriteS3 : SchedWriteRes<[M1UnitS]> { let Latency = 3; }
@@ -140,10 +141,10 @@ def M1WriteSD : SchedWriteRes<[M1UnitS,
def M1WriteSE : SchedWriteRes<[M1UnitS,
M1UnitA]> { let Latency = 2;
let NumMicroOps = 2; }
-def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteS1]>,
- SchedVar<NoSchedPred, [M1WriteSE]>]>;
-def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteS1]>,
- SchedVar<NoSchedPred, [M1WriteSB]>]>;
+def M1WriteSX : SchedWriteVariant<[SchedVar<M1LdStExtPred, [M1WriteS1]>,
+ SchedVar<NoSchedPred, [M1WriteSE]>]>;
+def M1WriteSY : SchedWriteVariant<[SchedVar<M1LdStExtPred, [M1WriteS1]>,
+ SchedVar<NoSchedPred, [M1WriteSB]>]>;
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 7b3ab72ccd0..e61fb611ab2 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -114,6 +114,7 @@ def M3RotatePred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
MI->getOpcode() == AArch64::EXTRXrri) &&
MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
+def M3LdStExtPred : SchedPredicate<[{TII->isExynosLdStExtFast(*MI)}]>;
def M3ShiftExtPred : SchedPredicate<[{TII->isExynosShiftExtFast(*MI)}]>;
//===----------------------------------------------------------------------===//
@@ -165,8 +166,8 @@ def M3WriteLD : SchedWriteRes<[M3UnitA,
def M3WriteLH : SchedWriteRes<[]> { let Latency = 5;
let NumMicroOps = 0; }
-def M3WriteLX : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteL5]>,
- SchedVar<NoSchedPred, [M3WriteLB]>]>;
+def M3WriteLX : SchedWriteVariant<[SchedVar<M3LdStExtPred, [M3WriteL5]>,
+ SchedVar<NoSchedPred, [M3WriteLB]>]>;
def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; }
def M3WriteSA : SchedWriteRes<[M3UnitA,
@@ -180,10 +181,10 @@ def M3WriteSC : SchedWriteRes<[M3UnitA,
M3UnitS]> { let Latency = 2;
let NumMicroOps = 2; }
-def M3WriteSX : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteS1]>,
- SchedVar<NoSchedPred, [M3WriteSB]>]>;
-def M3WriteSY : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteS1]>,
- SchedVar<NoSchedPred, [M3WriteSC]>]>;
+def M3WriteSX : SchedWriteVariant<[SchedVar<M3LdStExtPred, [M3WriteS1]>,
+ SchedVar<NoSchedPred, [M3WriteSB]>]>;
+def M3WriteSY : SchedWriteVariant<[SchedVar<M3LdStExtPred, [M3WriteS1]>,
+ SchedVar<NoSchedPred, [M3WriteSC]>]>;
def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
SchedVar<NoSchedPred, [ReadDefault]>]>;
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