diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 2 |
3 files changed, 11 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 7fc9c80f351..7721e897060 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -91,6 +91,11 @@ def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", "CustomAsCheapAsMove", "true", "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">; +def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", + "ExynosAsCheapAsMove", "true", + "Use Exynos specific code in TargetInstrInfo::isAsCheapAsAMove()", + [FeatureCustomCheapAsMoveHandling]>; + def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; @@ -311,7 +316,7 @@ def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", [FeatureSlowPaired128, FeatureCRC, FeatureCrypto, - FeatureCustomCheapAsMoveHandling, + FeatureExynosCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, @@ -326,7 +331,7 @@ def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1", [FeatureSlowPaired128, FeatureCRC, FeatureCrypto, - FeatureCustomCheapAsMoveHandling, + FeatureExynosCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, @@ -339,7 +344,7 @@ def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", "Samsung Exynos-M3 processors", [FeatureCRC, FeatureCrypto, - FeatureCustomCheapAsMoveHandling, + FeatureExynosCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureFuseLiterals, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 55a2e963d2b..0ab236e0aa1 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -676,8 +676,7 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { if (!Subtarget.hasCustomCheapAsMoveHandling()) return MI.isAsCheapAsAMove(); - if (Subtarget.getProcFamily() == AArch64Subtarget::ExynosM1 || - Subtarget.getProcFamily() == AArch64Subtarget::ExynosM3) { + if (Subtarget.hasExynosCheapAsMoveHandling()) { if (isExynosResetFast(MI) || isExynosShiftLeftFast(MI)) return true; else diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index ae55f3e2460..9b96bfa7f34 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -103,6 +103,7 @@ protected: bool PredictableSelectIsExpensive = false; bool BalanceFPOps = false; bool CustomAsCheapAsMove = false; + bool ExynosAsCheapAsMove = false; bool UsePostRAScheduler = false; bool Misaligned128StoreIsSlow = false; bool Paired128IsSlow = false; @@ -226,6 +227,7 @@ public: return PredictableSelectIsExpensive; } bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; } + bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; } bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; } bool isPaired128Slow() const { return Paired128IsSlow; } bool isSTRQroSlow() const { return STRQroIsSlow; } |
