diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIDefines.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 |
5 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 64d494b70d8..e4fbd956d65 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -613,6 +613,11 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4); OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4); } + + OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4); + OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4); + OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4); + OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4); } // This is supposed to be log2(Size) diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 5628c9e10ce..54efdc0a046 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -308,5 +308,7 @@ enum WidthMinusOne { // WidthMinusOne, (5) [15:11] #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) +#define R_SPILLED_SGPRS 0x4 +#define R_SPILLED_VGPRS 0x8 #endif diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 2c478d5213e..4d12a1ef9a9 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -63,6 +63,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) HasSpilledVGPRs(false), HasNonSpillStackObjects(false), HasFlatInstructions(false), + NumSpilledSGPRs(0), + NumSpilledVGPRs(0), PrivateSegmentBuffer(false), DispatchPtr(false), QueuePtr(false), diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 33d41926440..f5bd6366c71 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -85,6 +85,9 @@ private: bool HasNonSpillStackObjects; bool HasFlatInstructions; + unsigned NumSpilledSGPRs; + unsigned NumSpilledVGPRs; + // Feature bits required for inputs passed in user SGPRs. bool PrivateSegmentBuffer : 1; bool DispatchPtr : 1; @@ -313,6 +316,22 @@ public: HasFlatInstructions = UseFlat; } + unsigned getNumSpilledSGPRs() const { + return NumSpilledSGPRs; + } + + unsigned getNumSpilledVGPRs() const { + return NumSpilledVGPRs; + } + + void addToSpilledSGPRs(unsigned num) { + NumSpilledSGPRs += num; + } + + void addToSpilledVGPRs(unsigned num) { + NumSpilledVGPRs += num; + } + unsigned getPSInputAddr() const { return PSInputAddr; } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 2db5145c990..0dd88ee45c5 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -573,6 +573,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, } } MI->eraseFromParent(); + MFI->addToSpilledSGPRs(NumSubRegs); break; } @@ -642,6 +643,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, FrameInfo->getObjectOffset(Index) + TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS); MI->eraseFromParent(); + MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode())); break; case AMDGPU::SI_SPILL_V32_RESTORE: case AMDGPU::SI_SPILL_V64_RESTORE: |
