diff options
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 13 |
3 files changed, 27 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 99251bb23b1..e911085d0ad 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -238,6 +238,8 @@ bool IRTranslator::translateCompare(const User &U, bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) { const ReturnInst &RI = cast<ReturnInst>(U); const Value *Ret = RI.getReturnValue(); + if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0) + Ret = nullptr; // The target may mess up with the insertion point, but // this is not important as a return is the last instruction // of the block anyway. @@ -337,6 +339,9 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) { : MachineMemOperand::MONone; Flags |= MachineMemOperand::MOLoad; + if (DL->getTypeStoreSize(LI.getType()) == 0) + return true; + unsigned Res = getOrCreateVReg(LI); unsigned Addr = getOrCreateVReg(*LI.getPointerOperand()); @@ -355,6 +360,9 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) { : MachineMemOperand::MONone; Flags |= MachineMemOperand::MOStore; + if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0) + return true; + unsigned Val = getOrCreateVReg(*SI.getValueOperand()); unsigned Addr = getOrCreateVReg(*SI.getPointerOperand()); @@ -1269,8 +1277,11 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) { // Lower the actual args into this basic block. SmallVector<unsigned, 8> VRegArgs; - for (const Argument &Arg: F.args()) + for (const Argument &Arg: F.args()) { + if (DL->getTypeStoreSize(Arg.getType()) == 0) + continue; // Don't handle zero sized types. VRegArgs.push_back(getOrCreateVReg(Arg)); + } if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) { OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure", MF->getFunction()->getSubprogram(), diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp index 5cc8881d1c1..838305858ea 100644 --- a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp @@ -259,6 +259,8 @@ bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, SmallVector<ArgInfo, 8> SplitArgs; unsigned i = 0; for (auto &Arg : F.args()) { + if (DL.getTypeStoreSize(Arg.getType()) == 0) + continue; ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); bool Split = false; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 7c67a22e23c..7362bd817cc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1636,3 +1636,16 @@ define i32 @test_target_mem_intrinsic(i32* %addr) { } declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind + +%zerosize_type = type {} + +define %zerosize_type @test_empty_load_store(%zerosize_type *%ptr, %zerosize_type %in) noinline optnone { +; CHECK-LABEL: name: test_empty_load_store +; CHECK-NOT: G_STORE +; CHECK-NOT: G_LOAD +; CHECK: RET_ReallyLR +entry: + store %zerosize_type undef, %zerosize_type* undef, align 4 + %val = load %zerosize_type, %zerosize_type* %ptr, align 4 + ret %zerosize_type %in +} |
