diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86FastISel.cpp | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 9c81be1622a..32f03998a60 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -3512,16 +3512,6 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) { report_fatal_error("SSE register return with SSE disabled"); } - // If the return value is an i1 and AVX-512 is enabled, we need - // to do a fixup to make the copy legal. - if (CopyVT == MVT::i1 && SrcReg == X86::AL && Subtarget->hasAVX512()) { - // Need to copy to a GR32 first. - // TODO: MOVZX isn't great here. We don't care about the upper bits. - SrcReg = createResultReg(&X86::GR32RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(X86::MOVZX32rr8), SrcReg).addReg(X86::AL); - } - // If we prefer to use the value in xmm registers, copy it out as f80 and // use a truncate to move it from fp stack reg to xmm reg. if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) && |
