6 files changed, 20 insertions, 0 deletions

diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index b79ba83dc1b..9d9822c3d07 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -387,6 +387,7 @@ struct MachineFunction {
   // GISel MachineFunctionProperties.
   bool Legalized = false;
   bool RegBankSelected = false;
+  bool Selected = false;
   // Register information
   bool IsSSA = false;
   bool TracksRegLiveness = false;
@@ -413,6 +414,7 @@ template <> struct MappingTraits<MachineFunction> {
     YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
     YamlIO.mapOptional("legalized", MF.Legalized);
     YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
+    YamlIO.mapOptional("selected", MF.Selected);
     YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 93bacbc2d4f..f4c3b5c9ebb 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -124,12 +124,20 @@ public:
   //   - legal pre-isel generic instructions.
   // RegBankSelected: In GlobalISel: the RegBankSelect pass ran and all generic
   //  virtual registers have been assigned to a register bank.
+  // Selected: In GlobalISel: the InstructionSelect pass ran and all pre-isel
+  //  generic instructions have been eliminated; i.e., all instructions are now
+  //  target-specific or non-pre-isel generic instructions (e.g., COPY).
+  //  Since only pre-isel generic instructions can have generic virtual register
+  //  operands, this also means that all generic virtual registers have been
+  //  constrained to virtual registers (assigned to register classes) and that
+  //  all sizes attached to them have been eliminated.
   enum class Property : unsigned {
     IsSSA,
     TracksLiveness,
     AllVRegsAllocated,
     Legalized,
     RegBankSelected,
+    Selected,
     LastProperty,
   };
 
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index fcec6deb100..7c460b60ac6 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -298,6 +298,8 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   if (YamlMF.RegBankSelected)
     MF.getProperties().set(
         MachineFunctionProperties::Property::RegBankSelected);
+  if (YamlMF.Selected)
+    MF.getProperties().set(MachineFunctionProperties::Property::Selected);
 
   PerFunctionMIParsingState PFS(MF, SM, IRSlots);
   if (initializeRegisterInfo(PFS, YamlMF))
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index d08feec0046..d66ac0153c2 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -182,6 +182,8 @@ void MIRPrinter::print(const MachineFunction &MF) {
       MachineFunctionProperties::Property::Legalized);
   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
+  YamlMF.Selected = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::Selected);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 6cd3b65b294..c84faafaa48 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -82,6 +82,9 @@ void MachineFunctionProperties::print(raw_ostream &ROS, bool OnlySet) const {
       case Property::RegBankSelected:
         ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
         break;
+      case Property::Selected:
+        ROS << (HasProperty ? "" : "not ") << "selected";
+        break;
       default:
         break;
     }
diff --git a/llvm/test/CodeGen/MIR/Generic/global-isel-properties.mir b/llvm/test/CodeGen/MIR/Generic/global-isel-properties.mir
index ef2d1da6828..1384632afd0 100644
--- a/llvm/test/CodeGen/MIR/Generic/global-isel-properties.mir
+++ b/llvm/test/CodeGen/MIR/Generic/global-isel-properties.mir
@@ -21,6 +21,7 @@
 # CHECK-LABEL: name: test_defaults
 # CHECK:      legalized: false
 # CHECK-NEXT: regBankSelected: false
+# CHECK-NEXT: selected: false
 name:            test_defaults
 body: |
   bb.0:
@@ -29,9 +30,11 @@ body: |
 # CHECK-LABEL: name: test
 # CHECK:      legalized: true
 # CHECK-NEXT: regBankSelected: true
+# CHECK-NEXT: selected: true
 name: test
 legalized: true
 regBankSelected: true
+selected: true
 body: |
   bb.0:
 ...