diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/bitcast-int-to-vector.ll | 10 |
2 files changed, 12 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b4299f4ff85..b423d68e0f0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4212,7 +4212,8 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { unsigned NumElts = MVT::getVectorNumElements(VT); if (InVec.getOpcode() == ISD::BIT_CONVERT) { MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); - if (NumElts != MVT::getVectorNumElements(BCVT)) + if (!MVT::isVector(BCVT) || + NumElts != MVT::getVectorNumElements(BCVT)) return SDOperand(); InVec = InVec.getOperand(0); EVT = MVT::getVectorElementType(BCVT); diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll new file mode 100644 index 00000000000..370bec09848 --- /dev/null +++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86 + +define i1 @foo(i64 %a) +{ + %t = bitcast i64 %a to <2 x float> + %r = extractelement <2 x float> %t, i32 0 + %s = extractelement <2 x float> %t, i32 1 + %b = fcmp uno float %r, %s + ret i1 %b +} |
