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-rw-r--r--llvm/include/llvm/MC/MCSchedule.h5
-rw-r--r--llvm/lib/CodeGen/TargetSchedule.cpp10
-rw-r--r--llvm/lib/MC/MCSchedule.cpp17
3 files changed, 23 insertions, 9 deletions
diff --git a/llvm/include/llvm/MC/MCSchedule.h b/llvm/include/llvm/MC/MCSchedule.h
index b6afab96067..f1f5f3ffc9c 100644
--- a/llvm/include/llvm/MC/MCSchedule.h
+++ b/llvm/include/llvm/MC/MCSchedule.h
@@ -21,6 +21,7 @@
namespace llvm {
struct InstrItinerary;
+class MCSubtargetInfo;
/// Define a kind of processor resource that will be modeled by the scheduler.
struct MCProcResourceDesc {
@@ -226,6 +227,10 @@ struct MCSchedModel {
return &SchedClassTable[SchedClassIdx];
}
+ /// Returns the latency value for the scheduling class.
+ static int computeInstrLatency(const MCSubtargetInfo &STI,
+ const MCSchedClassDesc &SCDesc);
+
/// Returns the default initialized model.
static const MCSchedModel &GetDefaultSchedModel() { return Default; }
static const MCSchedModel Default;
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index 7d636b126e0..432545bde1f 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -257,15 +257,7 @@ unsigned TargetSchedModel::computeOperandLatency(
unsigned
TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
- unsigned Latency = 0;
- for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
- DefIdx != DefEnd; ++DefIdx) {
- // Lookup the definition's write latency in SubtargetInfo.
- const MCWriteLatencyEntry *WLEntry =
- STI->getWriteLatencyEntry(&SCDesc, DefIdx);
- Latency = std::max(Latency, capLatency(WLEntry->Cycles));
- }
- return Latency;
+ return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
}
unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp
index f3919427bf0..653049cc267 100644
--- a/llvm/lib/MC/MCSchedule.cpp
+++ b/llvm/lib/MC/MCSchedule.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCSchedule.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include <type_traits>
using namespace llvm;
@@ -32,3 +33,19 @@ const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
0,
0,
nullptr};
+
+int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
+ const MCSchedClassDesc &SCDesc) {
+ int Latency = 0;
+ for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
+ DefIdx != DefEnd; ++DefIdx) {
+ // Lookup the definition's write latency in SubtargetInfo.
+ const MCWriteLatencyEntry *WLEntry =
+ STI.getWriteLatencyEntry(&SCDesc, DefIdx);
+ // Early exit if we found an invalid latency.
+ if (WLEntry->Cycles < 0)
+ return WLEntry->Cycles;
+ Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
+ }
+ return Latency;
+}
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