Added support for LWU microMIPS instruction.

llvm-svn: 199315

4 files changed, 21 insertions, 0 deletions

diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 84cba5fb20e..ffcf48bf98d 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -60,6 +60,16 @@ class SCBaseMM<string opstr, RegisterOperand RO> :
   let Constraints = "$rt = $dst";
 }
 
+class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
+             InstrItinClass Itin = NoItinerary> :
+  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
+         !strconcat(opstr, "\t$rt, $addr"),
+         [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMImm12";
+  let canFoldAsLoad = 1;
+  let mayLoad = 1;
+}
+
 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   /// Arithmetic Instructions (ALU Immediate)
   def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
@@ -136,6 +146,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
     def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
   }
 
+  def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, IILoad>, LL_FM_MM<0xe>;
+
   /// Load and Store Instructions - unaligned
   def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
                LWL_FM_MM<0x0>;
diff --git a/llvm/test/MC/Disassembler/Mips/micromips.txt b/llvm/test/MC/Disassembler/Mips/micromips.txt
index b2d0cc02fc7..91d06162a18 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips.txt
@@ -145,6 +145,9 @@
 # CHECK: sw  $5, 4($6)
 0xf8 0xa6 0x00 0x04
 
+# CHECK: lwu $2, 8($4)
+0x60 0x44 0xe0 0x08
+
 # CHECK: lwl $4, 16($5)
 0x60 0x85 0x00 0x10
 
diff --git a/llvm/test/MC/Disassembler/Mips/micromips_le.txt b/llvm/test/MC/Disassembler/Mips/micromips_le.txt
index 5b2fe30dd06..f32eb38c149 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips_le.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips_le.txt
@@ -145,6 +145,9 @@
 # CHECK: sw $5, 4($6)
 0xa6 0xf8 0x04 0x00
 
+# CHECK: lwu $2, 8($4)
+0x44 0x60 0x08 0xe0
+
 # CHECK: lwl $4, 16($5)
 0x85 0x60 0x10 0x00
 
diff --git a/llvm/test/MC/Mips/micromips-loadstore-instructions.s b/llvm/test/MC/Mips/micromips-loadstore-instructions.s
index 4885e4e34d8..8a1b93babdd 100644
--- a/llvm/test/MC/Mips/micromips-loadstore-instructions.s
+++ b/llvm/test/MC/Mips/micromips-loadstore-instructions.s
@@ -19,6 +19,7 @@
 # CHECK-EL: sw     $5, 4($6)      # encoding: [0xa6,0xf8,0x04,0x00]
 # CHECK-EL: ll     $2, 8($4)      # encoding: [0x44,0x60,0x08,0x30]
 # CHECK-EL: sc     $2, 8($4)      # encoding: [0x44,0x60,0x08,0xb0]
+# CHECK-EL: lwu    $2, 8($4)      # encoding: [0x44,0x60,0x08,0xe0]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -32,6 +33,7 @@
 # CHECK-EB: sw     $5, 4($6)      # encoding: [0xf8,0xa6,0x00,0x04]
 # CHECK-EB: ll     $2, 8($4)      # encoding: [0x60,0x44,0x30,0x08]
 # CHECK-EB: sc     $2, 8($4)      # encoding: [0x60,0x44,0xb0,0x08]
+# CHECK-EB: lwu    $2, 8($4)      # encoding: [0x60,0x44,0xe0,0x08]
      lb     $5, 8($4)
      lbu    $6, 8($4)
      lh     $2, 8($4)
@@ -42,3 +44,4 @@
      sw     $5, 4($6)
      ll     $2, 8($4)
      sc     $2, 8($4)
+     lwu    $2, 8($4)