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authorJim Grosbach <grosbach@apple.com>2010-09-29 17:32:29 +0000
committerJim Grosbach <grosbach@apple.com>2010-09-29 17:32:29 +0000
commitc7b10f3745c94d1c2e1fc1f1ae8a6083e2ec3e32 (patch)
tree6b55cfd750168f1d1ee0f437058501318008938d /llvm
parent3801fbdee806a2ff70f4c442a4f4fcb2b757c836 (diff)
downloadbcm5719-llvm-c7b10f3745c94d1c2e1fc1f1ae8a6083e2ec3e32.tar.gz
bcm5719-llvm-c7b10f3745c94d1c2e1fc1f1ae8a6083e2ec3e32.zip
Add braces for legibility.
llvm-svn: 115043
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index bcaf6623393..7bc7b4ae01b 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -289,7 +289,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
}
// Match simple R +/- imm12 operands.
- if (N.getOpcode() == ISD::ADD)
+ if (N.getOpcode() == ISD::ADD) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
int RHSC = (int)RHS->getZExtValue();
if ((RHSC >= 0 && RHSC < 0x1000) ||
@@ -312,6 +312,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue N,
return true;
}
}
+ }
// Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
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