[AArch64] add tests for bitcasted DUPLANE; NFC

See D63815 for context/motivation.

1 files changed, 40 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
index 8e8cee28678..5eec06f552d 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
@@ -1660,6 +1660,46 @@ entry:
   ret <2 x float> %mul
 }
 
+define <2 x float> @test_vmul_laneq3_f32_bitcast(<2 x float> %a, <2 x double> %v) {
+; CHECK-LABEL: test_vmul_laneq3_f32_bitcast:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT:    fmul v0.2s, v0.2s, v1.s[1]
+; CHECK-NEXT:    ret
+  %extract = shufflevector <2 x double> %v, <2 x double> undef, <1 x i32> <i32 1>
+  %bc = bitcast <1 x double> %extract to <2 x float>
+  %splat = shufflevector <2 x float> %bc, <2 x float> undef, <2 x i32> <i32 1, i32 1>
+  %mul = fmul <2 x float> %splat, %a
+  ret <2 x float> %mul
+}
+
+define <2 x float> @test_vmul_laneq2_f32_bitcast(<2 x float> %a, <2 x double> %v) {
+; CHECK-LABEL: test_vmul_laneq2_f32_bitcast:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT:    fmul v0.2s, v0.2s, v1.s[0]
+; CHECK-NEXT:    ret
+  %extract = shufflevector <2 x double> %v, <2 x double> undef, <1 x i32> <i32 1>
+  %bc = bitcast <1 x double> %extract to <2 x float>
+  %splat = shufflevector <2 x float> %bc, <2 x float> undef, <2 x i32> <i32 0, i32 0>
+  %mul = fmul <2 x float> %splat, %a
+  ret <2 x float> %mul
+}
+
+define <4 x i16> @test_vmul_laneq5_i16_bitcast(<4 x i16> %a, <2 x double> %v) {
+; CHECK-LABEL: test_vmul_laneq5_i16_bitcast:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT:    dup v1.4h, v1.h[1]
+; CHECK-NEXT:    add v0.4h, v1.4h, v0.4h
+; CHECK-NEXT:    ret
+  %extract = shufflevector <2 x double> %v, <2 x double> undef, <1 x i32> <i32 1>
+  %bc = bitcast <1 x double> %extract to <4 x i16>
+  %splat = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %r = add <4 x i16> %splat, %a
+  ret <4 x i16> %r
+}
+
 define <1 x double> @test_vmul_laneq_f64(<1 x double> %a, <2 x double> %v) {
 ; CHECK-LABEL: test_vmul_laneq_f64:
 ; CHECK:       // %bb.0: // %entry