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authorDan Gohman <dan433584@gmail.com>2015-11-13 00:40:37 +0000
committerDan Gohman <dan433584@gmail.com>2015-11-13 00:40:37 +0000
commitb1daa3aec7e2f9265133d34ad7242c553fa888f6 (patch)
treef2fd75eaf5ea02ca316793f1b7542877f7f12fa8 /llvm
parent149c433bcc3690670909407d9c460baa9351ae27 (diff)
downloadbcm5719-llvm-b1daa3aec7e2f9265133d34ad7242c553fa888f6.tar.gz
bcm5719-llvm-b1daa3aec7e2f9265133d34ad7242c553fa888f6.zip
[WebAssembly] Tidy up and update a TODO item. NFC.
llvm-svn: 252984
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td23
1 files changed, 9 insertions, 14 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
index 2402bc52ed2..8751325839d 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td
@@ -33,22 +33,17 @@ def FP64 : WebAssemblyReg<"%FP64">;
def SP32 : WebAssemblyReg<"%SP32">;
def SP64 : WebAssemblyReg<"%SP64">;
-// TODO(jfb) The following comes from NVPTX. Is it really needed, or can we do
-// away with it? Try deleting once the backend works.
-// WebAssembly uses virtual registers, but the backend defines a few physical
-// registers here to keep SDAG and the MachineInstr layers happy.
-foreach i = 0-4 in {
- def I#i : WebAssemblyReg<"%i."#i>; // i32
- def L#i : WebAssemblyReg<"%l."#i>; // i64
- def F#i : WebAssemblyReg<"%f."#i>; // f32
- def D#i : WebAssemblyReg<"%d."#i>; // f64
-}
+// The register allocation framework requires register classes have at least
+// one register, so we define a few for the floating point register classes
+// since we otherwise don't need a physical register in those classes.
+def F32_0 : WebAssemblyReg<"%f32.0">;
+def F64_0 : WebAssemblyReg<"%f64.0">;
//===----------------------------------------------------------------------===//
// Register classes
//===----------------------------------------------------------------------===//
-def I32 : WebAssemblyRegClass<[i32], 32, (add (sequence "I%u", 0, 4), SP32)>;
-def I64 : WebAssemblyRegClass<[i64], 64, (add (sequence "L%u", 0, 4), SP64)>;
-def F32 : WebAssemblyRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
-def F64 : WebAssemblyRegClass<[f64], 64, (add (sequence "D%u", 0, 4))>;
+def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
+def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
+def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
+def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
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