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| author | Quentin Colombet <qcolombet@apple.com> | 2016-10-12 04:12:44 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2016-10-12 04:12:44 +0000 |
| commit | a907b5ca7c836fc67025adc1e68fcbc1e1293b6d (patch) | |
| tree | 2f0ceaae6a583030c26333ada556c74b96509817 /llvm | |
| parent | 9de30faeac08c368ecc50b74a69bf505096571aa (diff) | |
| download | bcm5719-llvm-a907b5ca7c836fc67025adc1e68fcbc1e1293b6d.tar.gz bcm5719-llvm-a907b5ca7c836fc67025adc1e68fcbc1e1293b6d.zip | |
[AArch64][InstructionSelector] Fix unintended test changes in r283973.
I screwed up my merge conflict and lost some of the CHECK lines.
llvm-svn: 283974
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index fd63ffda543..3f1d11d0b3a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -1447,15 +1447,18 @@ regBankSelected: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr64all } -# CHECK-NEXT: - { id: 1, class: gpr64all } +# CHECK-NEXT: - { id: 1, class: fpr64 } # CHECK-NEXT: - { id: 2, class: gpr64all } # CHECK-NEXT: - { id: 3, class: gpr64all } registers: - { id: 0, class: gpr } - - { id: 1, class: gpr } + - { id: 1, class: fpr } - { id: 2, class: gpr } - { id: 3, class: gpr } - # CHECK: %2 = COPY %0 +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %0 +# CHECK: %2 = COPY %0 # CHECK: %3 = COPY %2 body: | bb.0: |
