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| author | Craig Topper <craig.topper@gmail.com> | 2015-01-15 09:37:15 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2015-01-15 09:37:15 +0000 |
| commit | 9fdd078afbab5428b288c32bf7aa9e540cdeb4a7 (patch) | |
| tree | 5fad044a4741d9da1cb664588030a63669b46f23 /llvm | |
| parent | 962b0c7740684528755b08838766795c7e47308e (diff) | |
| download | bcm5719-llvm-9fdd078afbab5428b288c32bf7aa9e540cdeb4a7.tar.gz bcm5719-llvm-9fdd078afbab5428b288c32bf7aa9e540cdeb4a7.zip | |
Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.
llvm-svn: 226155
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index c4ec3df7b38..463ab623270 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2113,7 +2113,7 @@ multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat, multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag, ValueType OpVT, RegisterClass KRC, RegisterClass RC, X86MemOperand memop, Domain d> { - let isAsmParserOnly = 1, hasSideEffects = 0 in { + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>, EVEX; |
