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| author | Kevin Enderby <enderby@apple.com> | 2012-04-11 22:40:17 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2012-04-11 22:40:17 +0000 |
| commit | 72f18bbcffe3a57fc8f23c2f4e5aa5779eec0425 (patch) | |
| tree | b0a12997dd662d8c28a0585ba224b205cf747a8d /llvm | |
| parent | 918d52cc53f2a01f11f52bc2d8556469c640694e (diff) | |
| download | bcm5719-llvm-72f18bbcffe3a57fc8f23c2f4e5aa5779eec0425.tar.gz bcm5719-llvm-72f18bbcffe3a57fc8f23c2f4e5aa5779eec0425.zip | |
Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.
llvm-svn: 154544
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt | 13 |
2 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index e1d63fac906..05e3cedbdf5 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2410,6 +2410,8 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, case ARM::VST2b8wb_register: case ARM::VST2b16wb_register: case ARM::VST2b32wb_register: + if (Rm == 0xF) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::CreateImm(0)); break; case ARM::VST3d8_UPD: diff --git a/llvm/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/llvm/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt new file mode 100644 index 00000000000..8ff3a2b9bd5 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +0x00 0xf9 0x2f 0x06 |
