[AArch64][SVE] Asm: Support for predicated unary operations.

This patch adds support for the following instructions:
  CLS  (Count Leading Sign bits)
  CLZ  (Count Leading Zeros)
  CNT  (Count non-zero bits)
  CNOT (Logically invert boolean condition in vector)
  NOT  (Bitwise invert vector)
  FABS (Floating-point absolute value)
  FNEG (Floating-point negate)

All operations are predicated and unary, e.g.
  clz  z0.s, p0/m, z1.s

- CLS, CLZ, CNT, CNOT and NOT have variants for 8, 16, 32
  and 64 bit elements.

- FABS and FNEG have variants for 16, 32 and 64 bit elements.

llvm-svn: 336677

16 files changed, 375 insertions, 14 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 9c78f047690..6ae55aa51bb 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -66,6 +66,14 @@ let Predicates = [HasSVE] in {
   defm ABS_ZPmZ  : sve_int_un_pred_arit_0<  0b110, "abs">;
   defm NEG_ZPmZ  : sve_int_un_pred_arit_0<  0b111, "neg">;
 
+  defm CLS_ZPmZ  : sve_int_un_pred_arit_1<   0b000, "cls">;
+  defm CLZ_ZPmZ  : sve_int_un_pred_arit_1<   0b001, "clz">;
+  defm CNT_ZPmZ  : sve_int_un_pred_arit_1<   0b010, "cnt">;
+  defm CNOT_ZPmZ : sve_int_un_pred_arit_1<   0b011, "cnot">;
+  defm NOT_ZPmZ  : sve_int_un_pred_arit_1<   0b110, "not">;
+  defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">;
+  defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">;
+
   defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">;
   defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">;
   defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 39612a2001f..b3f71376421 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1159,8 +1159,8 @@ multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> {
 // SVE Integer Arithmetic - Unary Predicated Group
 //===----------------------------------------------------------------------===//
 
-class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
-                             ZPRRegOp zprty>
+class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
+                             string asm, ZPRRegOp zprty>
 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
@@ -1170,8 +1170,9 @@ class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
   bits<5> Zn;
   let Inst{31-24} = 0b00000100;
   let Inst{23-22} = sz8_64;
-  let Inst{21-19} = 0b010;
-  let Inst{18-16} = opc;
+  let Inst{21-20} = 0b01;
+  let Inst{19}    = opc{0};
+  let Inst{18-16} = opc{3-1};
   let Inst{15-13} = 0b101;
   let Inst{12-10} = Pg;
   let Inst{9-5}   = Zn;
@@ -1181,27 +1182,39 @@ class sve_int_un_pred_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
 }
 
 multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> {
-  def _B : sve_int_un_pred_arit_0<0b00, opc, asm, ZPR8>;
-  def _H : sve_int_un_pred_arit_0<0b01, opc, asm, ZPR16>;
-  def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
-  def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
+  def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>;
+  def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
+  def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
+  def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
 }
 
 multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> {
-  def _H : sve_int_un_pred_arit_0<0b01, opc, asm, ZPR16>;
-  def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
-  def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
+  def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
+  def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
+  def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
 }
 
 multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> {
-  def _S : sve_int_un_pred_arit_0<0b10, opc, asm, ZPR32>;
-  def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
+  def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
+  def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
 }
 
 multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> {
-  def _D : sve_int_un_pred_arit_0<0b11, opc, asm, ZPR64>;
+  def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
 }
 
+multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm> {
+  def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>;
+  def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
+  def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
+  def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
+}
+
+multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm> {
+  def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
+  def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
+  def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
+}
 
 //===----------------------------------------------------------------------===//
 // SVE Integer Wide Immediate - Unpredicated Group
diff --git a/llvm/test/MC/AArch64/SVE/cls-diagnostics.s b/llvm/test/MC/AArch64/SVE/cls-diagnostics.s
new file mode 100644
index 00000000000..fe5d15b42e6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cls-diagnostics.s
@@ -0,0 +1,18 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+cls     z31.b, p8/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cls     z31.b, p8/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+cls     z31.b, p7/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cls     z31.b, p7/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cls.s b/llvm/test/MC/AArch64/SVE/cls.s
new file mode 100644
index 00000000000..db1c0b2a7ce
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cls.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cls     z31.b, p7/m, z31.b
+// CHECK-INST: cls	z31.b, p7/m, z31.b
+// CHECK-ENCODING: [0xff,0xbf,0x18,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 18 04 <unknown>
+
+cls     z31.h, p7/m, z31.h
+// CHECK-INST: cls	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x58,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 58 04 <unknown>
+
+cls     z31.s, p7/m, z31.s
+// CHECK-INST: cls	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x98,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 98 04 <unknown>
+
+cls     z31.d, p7/m, z31.d
+// CHECK-INST: cls	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf d8 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/clz-diagnostics.s b/llvm/test/MC/AArch64/SVE/clz-diagnostics.s
new file mode 100644
index 00000000000..242b9330218
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/clz-diagnostics.s
@@ -0,0 +1,18 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+clz     z31.b, p8/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: clz     z31.b, p8/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+clz     z31.b, p7/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: clz     z31.b, p7/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/clz.s b/llvm/test/MC/AArch64/SVE/clz.s
new file mode 100644
index 00000000000..76e9d1bf83f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/clz.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+clz     z31.b, p7/m, z31.b
+// CHECK-INST: clz	z31.b, p7/m, z31.b
+// CHECK-ENCODING: [0xff,0xbf,0x19,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 19 04 <unknown>
+
+clz     z31.h, p7/m, z31.h
+// CHECK-INST: clz	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x59,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 59 04 <unknown>
+
+clz     z31.s, p7/m, z31.s
+// CHECK-INST: clz	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x99,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 99 04 <unknown>
+
+clz     z31.d, p7/m, z31.d
+// CHECK-INST: clz	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xd9,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf d9 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cnot-diagnostics.s b/llvm/test/MC/AArch64/SVE/cnot-diagnostics.s
new file mode 100644
index 00000000000..867b6bb005a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cnot-diagnostics.s
@@ -0,0 +1,18 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+cnot     z31.b, p8/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cnot     z31.b, p8/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+cnot     z31.b, p7/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cnot     z31.b, p7/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cnot.s b/llvm/test/MC/AArch64/SVE/cnot.s
new file mode 100644
index 00000000000..06ac6c8660d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cnot.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cnot    z31.b, p7/m, z31.b
+// CHECK-INST: cnot	z31.b, p7/m, z31.b
+// CHECK-ENCODING: [0xff,0xbf,0x1b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 1b 04 <unknown>
+
+cnot    z31.h, p7/m, z31.h
+// CHECK-INST: cnot	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x5b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5b 04 <unknown>
+
+cnot    z31.s, p7/m, z31.s
+// CHECK-INST: cnot	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x9b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9b 04 <unknown>
+
+cnot    z31.d, p7/m, z31.d
+// CHECK-INST: cnot	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xdb,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf db 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/cnt-diagnostics.s b/llvm/test/MC/AArch64/SVE/cnt-diagnostics.s
new file mode 100644
index 00000000000..8dcd62d7fbd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cnt-diagnostics.s
@@ -0,0 +1,18 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+cnt     z31.b, p8/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: cnt     z31.b, p8/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+cnt     z31.b, p7/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: cnt     z31.b, p7/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/cnt.s b/llvm/test/MC/AArch64/SVE/cnt.s
new file mode 100644
index 00000000000..4a81b1a9a9b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/cnt.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cnt     z31.b, p7/m, z31.b
+// CHECK-INST: cnt	z31.b, p7/m, z31.b
+// CHECK-ENCODING: [0xff,0xbf,0x1a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 1a 04 <unknown>
+
+cnt     z31.h, p7/m, z31.h
+// CHECK-INST: cnt	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x5a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5a 04 <unknown>
+
+cnt     z31.s, p7/m, z31.s
+// CHECK-INST: cnt	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x9a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9a 04 <unknown>
+
+cnt     z31.d, p7/m, z31.d
+// CHECK-INST: cnt	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xda,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf da 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fabs-diagnostics.s b/llvm/test/MC/AArch64/SVE/fabs-diagnostics.s
new file mode 100644
index 00000000000..755202fd325
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fabs-diagnostics.s
@@ -0,0 +1,23 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fabs    z31.h, p8/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fabs    z31.h, p8/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fabs    z31.b, p7/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fabs    z31.b, p7/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fabs    z31.h, p7/m, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fabs    z31.h, p7/m, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fabs.s b/llvm/test/MC/AArch64/SVE/fabs.s
new file mode 100644
index 00000000000..c9d4d8405be
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fabs.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fabs    z31.h, p7/m, z31.h
+// CHECK-INST: fabs	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x5c,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5c 04 <unknown>
+
+fabs    z31.s, p7/m, z31.s
+// CHECK-INST: fabs	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x9c,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9c 04 <unknown>
+
+fabs    z31.d, p7/m, z31.d
+// CHECK-INST: fabs	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xdc,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf dc 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/fneg-diagnostics.s b/llvm/test/MC/AArch64/SVE/fneg-diagnostics.s
new file mode 100644
index 00000000000..1ddcea44689
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fneg-diagnostics.s
@@ -0,0 +1,23 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+fneg    z31.h, p8/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: fneg    z31.h, p8/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+fneg    z31.b, p7/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fneg    z31.b, p7/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fneg    z31.h, p7/m, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: fneg    z31.h, p7/m, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/fneg.s b/llvm/test/MC/AArch64/SVE/fneg.s
new file mode 100644
index 00000000000..9b9ca9041fb
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/fneg.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+fneg    z31.h, p7/m, z31.h
+// CHECK-INST: fneg	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x5d,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5d 04 <unknown>
+
+fneg    z31.s, p7/m, z31.s
+// CHECK-INST: fneg	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x9d,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9d 04 <unknown>
+
+fneg    z31.d, p7/m, z31.d
+// CHECK-INST: fneg	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xdd,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf dd 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/not-diagnostics.s b/llvm/test/MC/AArch64/SVE/not-diagnostics.s
new file mode 100644
index 00000000000..e95066bcbfe
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/not-diagnostics.s
@@ -0,0 +1,18 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+not     z31.b, p8/m, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: not     z31.b, p8/m, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+not     z31.b, p7/m, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: not     z31.b, p7/m, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/not.s b/llvm/test/MC/AArch64/SVE/not.s
index cf1a1472ff2..67ebce236c2 100644
--- a/llvm/test/MC/AArch64/SVE/not.s
+++ b/llvm/test/MC/AArch64/SVE/not.s
@@ -7,6 +7,30 @@
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+not     z31.b, p7/m, z31.b
+// CHECK-INST: not	z31.b, p7/m, z31.b
+// CHECK-ENCODING: [0xff,0xbf,0x1e,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 1e 04 <unknown>
+
+not     z31.h, p7/m, z31.h
+// CHECK-INST: not	z31.h, p7/m, z31.h
+// CHECK-ENCODING: [0xff,0xbf,0x5e,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 5e 04 <unknown>
+
+not     z31.s, p7/m, z31.s
+// CHECK-INST: not	z31.s, p7/m, z31.s
+// CHECK-ENCODING: [0xff,0xbf,0x9e,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 9e 04 <unknown>
+
+not     z31.d, p7/m, z31.d
+// CHECK-INST: not	z31.d, p7/m, z31.d
+// CHECK-ENCODING: [0xff,0xbf,0xde,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf de 04 <unknown>
+
 not     p0.b, p0/z, p0.b
 // CHECK-INST: not     p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x42,0x00,0x25]