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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-27 17:29:13 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-27 17:29:13 +0000 |
| commit | 2a64d393ea9aa51d623cd7e04ed248dc265881d4 (patch) | |
| tree | 5cf7501c0d45422fc1ec54d2efcd91bfce80ebc4 /llvm | |
| parent | fb8ca8a1ec54a209bc101cedfa69815f78f165fc (diff) | |
| download | bcm5719-llvm-2a64d393ea9aa51d623cd7e04ed248dc265881d4.tar.gz bcm5719-llvm-2a64d393ea9aa51d623cd7e04ed248dc265881d4.zip | |
[X86] Remove BT/BTC/BTR/BTS rr/ri overrides
llvm-svn: 343241
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleAtom.td | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index 6063d1a1582..22a18fe8cfb 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -121,8 +121,8 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { let Latency = 2; let ResourceCycles = [2]; } -defm : X86WriteRes<WriteBitTest, [AtomPort01], 1, [1], 1>; -defm : X86WriteRes<WriteBitTestSet, [AtomPort01], 1, [1], 1>; +defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>; +defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>; // This is for simple LEAs with one or two input operands. def : WriteRes<WriteLEA, [AtomPort1]>; @@ -501,8 +501,7 @@ def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { let ResourceCycles = [1]; } def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; -def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r", - "BT(C|R|S)?(16|32|64)(rr|ri8)")>; +def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>; def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { let Latency = 5; |
