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| author | Kang Zhang <shkzhang@cn.ibm.com> | 2019-04-18 07:24:15 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2019-04-18 07:24:15 +0000 |
| commit | 009a21d2fdff9117cafc853a2fe7e8355d2d31cc (patch) | |
| tree | b1da08dadad6873449d0f57db75029e384715c28 /llvm | |
| parent | 4f471ee99098d06b3ad74cd5ee06f82737bcbbd6 (diff) | |
| download | bcm5719-llvm-009a21d2fdff9117cafc853a2fe7e8355d2d31cc.tar.gz bcm5719-llvm-009a21d2fdff9117cafc853a2fe7e8355d2d31cc.zip | |
[PowerPC] Fix wrong ElemSIze when calling isConsecutiveLS()
Summary:
This issue from the bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41177
When the two operands for BUILD_VECTOR are same, we will get assert error.
llvm::SDValue combineBVOfConsecutiveLoads(llvm::SDNode*, llvm::SelectionDAG&):
Assertion `!(InputsAreConsecutiveLoads && InputsAreReverseConsecutive) &&
"The loads cannot be both consecutive and reverse consecutive."' failed.
This error caused by the wrong ElemSIze when calling isConsecutiveLS(). We
should use `getScalarType().getStoreSize();` to get the ElemSize instread of
`getScalarSizeInBits() / 8`.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D60811
llvm-svn: 358644
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr41177.ll | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d5a5cc30e62..f95c88f5a3e 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -12175,7 +12175,7 @@ static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) { SDLoc dl(N); bool InputsAreConsecutiveLoads = true; bool InputsAreReverseConsecutive = true; - unsigned ElemSize = N->getValueType(0).getScalarSizeInBits() / 8; + unsigned ElemSize = N->getValueType(0).getScalarType().getStoreSize(); SDValue FirstInput = N->getOperand(0); bool IsRoundOfExtLoad = false; diff --git a/llvm/test/CodeGen/PowerPC/pr41177.ll b/llvm/test/CodeGen/PowerPC/pr41177.ll new file mode 100644 index 00000000000..52108442893 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr41177.ll @@ -0,0 +1,12 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s +; REQUIRES: asserts + +define protected swiftcc void @"$s22LanguageServerProtocol13HoverResponseV8contents5rangeAcA13MarkupContentV_SnyAA8PositionVGSgtcfC"() { + %1 = load <2 x i64>, <2 x i64>* undef, align 16 + %2 = load i1, i1* undef, align 8 + %3 = insertelement <2 x i1> undef, i1 %2, i32 0 + %4 = shufflevector <2 x i1> %3, <2 x i1> undef, <2 x i32> zeroinitializer + %5 = select <2 x i1> %4, <2 x i64> zeroinitializer, <2 x i64> %1 + store <2 x i64> %5, <2 x i64>* undef, align 8 + ret void +} |
