MachineVerifier: subregs so not require defs/valnos on every path

It is fine for subregister ranges to be undefined on some CFG paths as
we may have a "vregX:other_subreg<read-undef> =" def on that path. We
do not (and should not) have live segments for the subregister ranges.
The MachineVerifier should not complain about this.

This is a slight variant of http://llvm.org/PR27705

llvm-svn: 270290

2 files changed, 29 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 87303952371..eca988499cd 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1844,8 +1844,9 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
       SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
       const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
 
-      // All predecessors must have a live-out value.
-      if (!PVNI) {
+      // All predecessors must have a live-out value if this is not a
+      // subregister liverange.
+      if (!PVNI && LaneMask == 0) {
         report("Register not marked live out of predecessor", *PI);
         report_context(LR, Reg, LaneMask);
         report_context(*VNI);
diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
new file mode 100644
index 00000000000..4f8c69db019
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
@@ -0,0 +1,26 @@
+; RUN: llc -verify-machineinstrs -o /dev/null %s
+; We may have subregister live ranges that are undefined on some paths. The
+; verifier should not complain about this.
+target triple = "amdgcn--"
+
+define void @func() {
+B0:
+  br i1 undef, label %B1, label %B2
+
+B1:
+  br label %B2
+
+B2:
+  %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float undef>, %B0 ]
+  br i1 undef, label %B30.1, label %B30.2
+
+B30.1:
+  %sub = fsub <4 x float> %v0, undef
+  br label %B30.2
+
+B30.2:
+  %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ]
+  %ve0 = extractelement <4 x float> %v3, i32 0
+  store float %ve0, float addrspace(3)* undef, align 4
+  ret void
+}