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author | Matt Davis <Matthew.Davis@sony.com> | 2018-05-25 18:00:25 +0000 |
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committer | Matt Davis <Matthew.Davis@sony.com> | 2018-05-25 18:00:25 +0000 |
commit | 5b79ffc5bc716172bf6061ca679ccc702840a352 (patch) | |
tree | d5ca33567234a28cd9337cf3b9a2bb5d01f5fa19 /llvm/tools/llvm-mca/RetireControlUnit.cpp | |
parent | cb48efd585aa1d45f5673dbb54eb674b04bf91b9 (diff) | |
download | bcm5719-llvm-5b79ffc5bc716172bf6061ca679ccc702840a352.tar.gz bcm5719-llvm-5b79ffc5bc716172bf6061ca679ccc702840a352.zip |
[llvm-mca] Add the RetireStage.
Summary:
This class maintains the same logic as the original RetireControlUnit.
This is just an intermediate patch to make the RCU a Stage. Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface.
Reviewers: andreadb, RKSimon, courbet
Reviewed By: andreadb, courbet
Subscribers: javed.absar, mgorny, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47244
llvm-svn: 333292
Diffstat (limited to 'llvm/tools/llvm-mca/RetireControlUnit.cpp')
-rw-r--r-- | llvm/tools/llvm-mca/RetireControlUnit.cpp | 37 |
1 files changed, 15 insertions, 22 deletions
diff --git a/llvm/tools/llvm-mca/RetireControlUnit.cpp b/llvm/tools/llvm-mca/RetireControlUnit.cpp index 3ce7e3e2cc1..d4c42742c42 100644 --- a/llvm/tools/llvm-mca/RetireControlUnit.cpp +++ b/llvm/tools/llvm-mca/RetireControlUnit.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file implements methods declared by the RetireControlUnit interface. +/// This file simulates the hardware responsible for retiring instructions. /// //===----------------------------------------------------------------------===// @@ -22,10 +22,9 @@ using namespace llvm; namespace mca { -RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM, - DispatchStage *DS) +RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM) : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0), - AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0), Owner(DS) { + AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) { // Check if the scheduling model provides extra information about the machine // processor. If so, then use that information to set the reorder buffer size // and the maximum number of instructions retired per cycle. @@ -58,25 +57,19 @@ unsigned RetireControlUnit::reserveSlot(const InstRef &IR, return TokenID; } -void RetireControlUnit::cycleEvent() { - if (isEmpty()) - return; +const RetireControlUnit::RUToken &RetireControlUnit::peekCurrentToken() const { + return Queue[CurrentInstructionSlotIdx]; +} - unsigned NumRetired = 0; - while (!isEmpty()) { - if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle) - break; - RUToken &Current = Queue[CurrentInstructionSlotIdx]; - assert(Current.NumSlots && "Reserved zero slots?"); - assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue."); - if (!Current.Executed) - break; - Owner->notifyInstructionRetired(Current.IR); - CurrentInstructionSlotIdx += Current.NumSlots; - CurrentInstructionSlotIdx %= Queue.size(); - AvailableSlots += Current.NumSlots; - NumRetired++; - } +void RetireControlUnit::consumeCurrentToken() { + const RetireControlUnit::RUToken &Current = peekCurrentToken(); + assert(Current.NumSlots && "Reserved zero slots?"); + assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue."); + + // Update the slot index to be the next item in the circular queue. + CurrentInstructionSlotIdx += Current.NumSlots; + CurrentInstructionSlotIdx %= Queue.size(); + AvailableSlots += Current.NumSlots; } void RetireControlUnit::onInstructionExecuted(unsigned TokenID) { |