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| author | Craig Topper <craig.topper@intel.com> | 2017-09-02 18:53:46 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-02 18:53:46 +0000 |
| commit | 619b759a57806a516911927f9940642eab20c037 (patch) | |
| tree | f861abd94cc73a8dd175416056885543c92c391b /llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp | |
| parent | bc6da4e40f6b389c4675812350bf096790591e8c (diff) | |
| download | bcm5719-llvm-619b759a57806a516911927f9940642eab20c037.tar.gz bcm5719-llvm-619b759a57806a516911927f9940642eab20c037.zip | |
[X86] Teach fastisel to handle zext/sext i8->i16 and sext i1->i8/i16/i32/i64
Summary:
ZExt and SExt from i8 to i16 aren't implemented in the autogenerated fast isel table because normal isel does a zext/sext to 32-bits and a subreg extract to avoid a partial register write or false dependency on the upper bits of the destination. This means without handling in fast isel we end up triggering a fast isel abort.
We had no custom sign extend handling at all so while I was there I went ahead and implemented sext i1->i8/i16/i32/i64 which was also missing. This generates an i1->i8 sign extend using a mask with 1, then an 8-bit negate, then continues with a sext from i8. A better sequence would be a wider and/negate, but would require more custom code.
Fast isel tests are a mess and I couldn't find a good home for the tests so I created a new one.
The test pr34381.ll had to have fast-isel removed because it was relying on a fast isel abort to hit the bug. The test case still seems valid with fast-isel disabled though some of the instructions changed.
Reviewers: spatel, zvi, igorb, guyblank, RKSimon
Reviewed By: guyblank
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37320
llvm-svn: 312422
Diffstat (limited to 'llvm/tools/llvm-isel-fuzzer/llvm-isel-fuzzer.cpp')
0 files changed, 0 insertions, 0 deletions
