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| author | Zvi Rackover <zvi.rackover@intel.com> | 2018-01-24 01:36:40 +0000 |
|---|---|---|
| committer | Zvi Rackover <zvi.rackover@intel.com> | 2018-01-24 01:36:40 +0000 |
| commit | b5447b1e7c3414ddc3998970cfbd2ec84420e1a9 (patch) | |
| tree | a19c74ecfcbfc5e4f7fa883c052cbb8063871eb7 /llvm/test | |
| parent | f2aa2af24e9d635189ffbc0ea797977e845466e9 (diff) | |
| download | bcm5719-llvm-b5447b1e7c3414ddc3998970cfbd2ec84420e1a9.tar.gz bcm5719-llvm-b5447b1e7c3414ddc3998970cfbd2ec84420e1a9.zip | |
X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW
Summary:
AVX512BW adds support for variable shift amount for 16-bit element
vectors.
Reviewers: craig.topper, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: rengolin, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D42437
llvm-svn: 323292
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll | 38 |
1 files changed, 28 insertions, 10 deletions
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll index 1fed90159c0..45c0b6e155a 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll @@ -29,16 +29,34 @@ if_false: } define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) { -; CHECK-LABEL: @test_16bit( -; CHECK-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer -; CHECK-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] -; CHECK: if_true: -; CHECK-NEXT: ret <8 x i16> [[MASK]] -; CHECK: if_false: -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]] -; CHECK-NEXT: ret <8 x i16> [[RES]] -; +; CHECK-SSE2-LABEL: @test_16bit +; CHECK-SSE2: if_true: +; CHECK-SSE2-NOT: shufflevector +; CHECK-SSE2: if_false: +; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK-SSE2: shl <8 x i16> %lhs, [[SPLAT]] + +; CHECK-AVX2-LABEL: @test_16bit +; CHECK-AVX2: if_true: +; CHECK-AVX2-NOT: shufflevector +; CHECK-AVX2: if_false: +; CHECK-AVX2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK-AVX2: shl <8 x i16> %lhs, [[SPLAT]] + +; CHECK-XOP-LABEL: @test_16bit +; CHECK-XOP: if_true: +; CHECK-XOP-NOT: shufflevector +; CHECK-XOP: if_false: +; CHECK-XOP: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK-XOP: shl <8 x i16> %lhs, [[SPLAT]] + +; CHECK-AVX512BW-LABEL: @test_16bit +; CHECK-AVX512BW: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector +; CHECK-AVX512BW: if_true: +; CHECK-AVX512BW-NOT: shufflevector +; CHECK-AVX512BW: if_false: +; CHECK-AVX512BW-NOT: shufflevector +; CHECK-AVX512BW: shl <8 x i16> %lhs, [[SPLAT]] %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer br i1 %tst, label %if_true, label %if_false |
