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| author | Craig Topper <craig.topper@intel.com> | 2017-08-20 21:38:28 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-20 21:38:28 +0000 |
| commit | a152903c1be57b863e2d6f3050564f4ec2602a26 (patch) | |
| tree | 5d219d36824987810d8f0541212512589eb2bde0 /llvm/test | |
| parent | d091bf8d8e1bd8337fd69abd95c3dd04797b4de1 (diff) | |
| download | bcm5719-llvm-a152903c1be57b863e2d6f3050564f4ec2602a26.tar.gz bcm5719-llvm-a152903c1be57b863e2d6f3050564f4ec2602a26.zip | |
[InstCombine] Add a test case for a weakness in canEvaluateZExtd. NFC
llvm-svn: 311303
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/cast.ll | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/cast.ll b/llvm/test/Transforms/InstCombine/cast.ll index e852c0ab5af..364337b9693 100644 --- a/llvm/test/Transforms/InstCombine/cast.ll +++ b/llvm/test/Transforms/InstCombine/cast.ll @@ -1586,3 +1586,22 @@ define i64 @test94(i32 %a) { %4 = sext i8 %3 to i64 ret i64 %4 } + +; We should be able to remove the zext and trunc here. +; TODO: This is currently blocked because we don't realize the 'and' has cleared the extra bits that would be shifted in widening the lshr. +define i32 @test95(i32 %x) { +; CHECK-LABEL: @test95( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8 +; CHECK-NEXT: [[TMP2:%.*]] = lshr i8 [[TMP1]], 6 +; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 2 +; CHECK-NEXT: [[TMP4:%.*]] = or i8 [[TMP3]], 40 +; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP4]] to i32 +; CHECK-NEXT: ret i32 [[TMP5]] +; + %1 = trunc i32 %x to i8 + %2 = lshr i8 %1, 6 + %3 = and i8 %2, 2 + %4 = or i8 %3, 40 + %5 = zext i8 %4 to i32 + ret i32 %5 +} |
