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| author | Tim Northover <tnorthover@apple.com> | 2014-04-28 11:27:43 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-28 11:27:43 +0000 |
| commit | 7b839f833d8c10f149da7fbfe97718505ffedf19 (patch) | |
| tree | 71017a8b7521a12e54cfe2add99ab41da3153baf /llvm/test | |
| parent | c00a7ff4b70c24b82069f5cb44477ccc8b9203cc (diff) | |
| download | bcm5719-llvm-7b839f833d8c10f149da7fbfe97718505ffedf19.tar.gz bcm5719-llvm-7b839f833d8c10f149da7fbfe97718505ffedf19.zip | |
ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.
Someone couldn't bear to have a completely orthogonal set of floating-point
registers, so we've got some instructions that only accept v0-v15 (coming in
ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...).
Anyway, we were permitting even the out of range registers during assembly
(CodeGen handled it correctly). This adds a diagnostic.
llvm-svn: 207412
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/ARM64/v128_lo-diagnostics.s | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM64/v128_lo-diagnostics.s b/llvm/test/MC/ARM64/v128_lo-diagnostics.s new file mode 100644 index 00000000000..ffe29cfbed3 --- /dev/null +++ b/llvm/test/MC/ARM64/v128_lo-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null +// RUN: FileCheck %s < %t + + sqrdmulh v0.8h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqrdmulh h0, h1, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqdmull2 v0.4h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction |
