[PPC] add absolute difference altivec instructions and matching intrinsics

This patch corresponds to review https://reviews.llvm.org/D26072.
Committing on behalf of Sean Fertile.

llvm-svn: 285627

3 files changed, 62 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/PowerPC/vec_absd.ll b/llvm/test/CodeGen/PowerPC/vec_absd.ll
new file mode 100644
index 00000000000..37a3a5c94a3
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vec_absd.ll
@@ -0,0 +1,40 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu  < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Check the vabsd* instructions that were added in PowerISA V3.0
+
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)
+
+; Function Attrs: nounwind readnone
+declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)
+
+define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {
+entry:
+  %res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+; CHECK-LABEL: @test_byte
+; CHECK: vabsdub 2, 2, 3
+; CHECK blr
+}
+
+define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
+entry:
+  %res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+; CHECK-LABEL: @test_half
+; CHECK: vabsduh 2, 2, 3
+; CHECK blr
+}
+
+define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+; CHECK-LABEL: @test_word
+; CHECK: vabsduw 2, 2, 3
+; CHECK: blr
+}
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
index b2b49765874..cb43a7c479a 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -838,6 +838,15 @@
 # CHECK: vmul10ecuq 2, 3, 4
 0x10 0x43 0x20 0x41
 
+#CHECK: vabsdub 2, 3, 4
+0x10 0x43 0x24 0x03
+
+#CHECK vabsduh 2, 3, 4
+0x10 0x43 0x24 0x43
+
+#CHECK vabsduw 2, 3, 4
+0x10 0x43 0x24 0x83
+
 # CHECK: bcdcfn. 27, 31, 1
 0x13 0x67 0xff 0x81
 
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
index 7ac4ce9e0d0..16c48a71e42 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -933,6 +933,19 @@
 # CHECK-LE: vmul10ecuq 2, 3, 4              # encoding: [0x41,0x20,0x43,0x10]
             vmul10ecuq 2, 3, 4
 
+# Vector Absolute Difference
+# CHECK-BE: vabsdub 2, 3, 4                # encoding: [0x10,0x43,0x24,0x03]
+# CHECK-LE: vabsdub 2, 3, 4                # encoding: [0x03,0x24,0x43,0x10]
+            vabsdub 2, 3, 4
+
+# CHECK-BE: vabsduh 2, 3, 4                # encoding: [0x10,0x43,0x24,0x43]
+# CHECK-LE: vabsduh 2, 3, 4                # encoding: [0x43,0x24,0x43,0x10]
+            vabsduh 2, 3, 4
+
+# CHECK-BE: vabsduw 2, 3, 4                # encoding: [0x10,0x43,0x24,0x83]
+# CHECK-LE: vabsduw 2, 3, 4                # encoding: [0x83,0x24,0x43,0x10]
+            vabsduw 2, 3, 4
+
 # Decimal Convert From/to National/Zoned/Signed-QWord
 # CHECK-BE: bcdcfn. 27, 31, 1                  # encoding: [0x13,0x67,0xff,0x81]
 # CHECK-LE: bcdcfn. 27, 31, 1                  # encoding: [0x81,0xff,0x67,0x13]