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| author | Jinsong Ji <jji@us.ibm.com> | 2019-06-24 18:00:34 +0000 |
|---|---|---|
| committer | Jinsong Ji <jji@us.ibm.com> | 2019-06-24 18:00:34 +0000 |
| commit | 318b6dafca23afd864d183b51b978a7ed9344416 (patch) | |
| tree | 04de145109809f1c9989448076ddc3c12198423c /llvm/test | |
| parent | 8fcd5ade3e5e9ca79180d72de47c99903511cc15 (diff) | |
| download | bcm5719-llvm-318b6dafca23afd864d183b51b978a7ed9344416.tar.gz bcm5719-llvm-318b6dafca23afd864d183b51b978a7ed9344416.zip | |
[PowerPC][UpdateTestChecks] powerpc- triple support
There are quite some old testcases with powerpc- triple,
we should add this triple support so that we can update them with script.
Differential Revision: https://reviews.llvm.org/D63723
llvm-svn: 364213
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/varargs.ll | 63 |
1 files changed, 33 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/PowerPC/varargs.ll b/llvm/test/CodeGen/PowerPC/varargs.ll index 807cf1168c3..0f28c1a0319 100644 --- a/llvm/test/CodeGen/PowerPC/varargs.ll +++ b/llvm/test/CodeGen/PowerPC/varargs.ll @@ -1,41 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck -check-prefix=P32 %s ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck -check-prefix=P64 %s ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix=P64 %s ; PR8327 define i8* @test1(i8** %foo) nounwind { +; P32-LABEL: test1: +; P32: # %bb.0: +; P32-NEXT: lbz r4, 0(r3) +; P32-NEXT: addi r5, r4, 1 +; P32-NEXT: stb r5, 0(r3) +; P32-NEXT: cmpwi r4, 8 +; P32-NEXT: lwz r5, 4(r3) +; P32-NEXT: slwi r4, r4, 2 +; P32-NEXT: addi r6, r5, 4 +; P32-NEXT: bc 12, lt, .LBB0_1 +; P32-NEXT: b .LBB0_2 +; P32-NEXT: .LBB0_1: +; P32-NEXT: addi r6, r5, 0 +; P32-NEXT: .LBB0_2: +; P32-NEXT: stw r6, 4(r3) +; P32-NEXT: lwz r3, 8(r3) +; P32-NEXT: add r3, r3, r4 +; P32-NEXT: bc 12, lt, .LBB0_4 +; P32-NEXT: # %bb.3: +; P32-NEXT: ori r3, r5, 0 +; P32-NEXT: b .LBB0_4 +; P32-NEXT: .LBB0_4: +; P32-NEXT: lwz r3, 0(r3) +; P32-NEXT: blr +; +; P64-LABEL: test1: +; P64: # %bb.0: +; P64-NEXT: ld r4, 0(r3) +; P64-NEXT: addi r5, r4, 8 +; P64-NEXT: std r5, 0(r3) +; P64-NEXT: ld r3, 0(r4) +; P64-NEXT: blr %A = va_arg i8** %foo, i8* ret i8* %A } -; P32-LABEL: test1: -; P32: lbz [[REG1:r[0-9]+]], 0(r3) -; P32: addi [[REG2:r[0-9]+]], [[REG1]], 1 -; P32: stb [[REG2]], 0(r3) -; P32: cmpwi [[REG1]], 8 -; P32: lwz [[REG3:r[0-9]+]], 4(r3) -; P32: slwi [[REG4:r[0-9]+]], [[REG1]], 2 -; P32: addi [[REG5:r[0-9]+]], [[REG3]], 4 -; P32: bc 12, lt, .LBB0_1 -; P32: b .LBB0_2 -; P32: .LBB0_1: -; P32: addi [[REG5]], [[REG3]], 0 -; P32: .LBB0_2: -; P32: stw [[REG5]], 4(r3) -; P32: lwz [[REG6:r[0-9]+]], 8(r3) -; P32: add [[REG6]], [[REG6]], [[REG4]] -; P32: bc 12, lt, .LBB0_4 -; P32: # %bb.3: -; P32: ori [[REG6]], [[REG2]], 0 -; P32: b .LBB0_4 -; P32: .LBB0_4: -; P32: lwz r3, 0([[REG6]]) -; P32: blr - -; P64-LABEL: test1: -; P64: ld [[REG1:r[0-9]+]], 0(r3) -; P64: addi [[REG2:r[0-9]+]], [[REG1]], 8 -; P64: std [[REG2]], 0(r3) -; P64: ld r3, 0([[REG1]]) -; P64: blr |
