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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2015-01-11 04:39:18 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2015-01-11 04:39:18 +0000 |
| commit | fe781977b9974b9669462df2ce8986258a25d080 (patch) | |
| tree | 79ac3ea06719e4273dabad57d35dc617ffb1d461 /llvm/test | |
| parent | 68fba279bc2e5671afd927ba13bc6a26ac62d750 (diff) | |
| download | bcm5719-llvm-fe781977b9974b9669462df2ce8986258a25d080.tar.gz bcm5719-llvm-fe781977b9974b9669462df2ce8986258a25d080.zip | |
ARM: add support for segment base relocations (SBREL)
This adds support for parsing and emitting the SBREL relocation variant for the
ARM target. Handling this relocation variant is necessary for supporting the
full ARM ELF specification. Addresses PR22128.
llvm-svn: 225595
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/ARM/arm-elf-relocation-diagnostics.s | 27 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/arm-elf-relocations.s | 10 |
2 files changed, 37 insertions, 0 deletions
diff --git a/llvm/test/MC/ARM/arm-elf-relocation-diagnostics.s b/llvm/test/MC/ARM/arm-elf-relocation-diagnostics.s new file mode 100644 index 00000000000..5fe903f7161 --- /dev/null +++ b/llvm/test/MC/ARM/arm-elf-relocation-diagnostics.s @@ -0,0 +1,27 @@ +@ RUN: not llvm-mc -triple armv7-eabi -filetype obj -o - %s 2>&1 \ +@ RUN: | FileCheck %s +@ RUN: not llvm-mc -triple thumbv7-eabi -filetype obj -o - %s 2>&1 \ +@ RUN: | FileCheck %s + + .byte target(sbrel) +@ CHECK: error: relocated expression must be 32-bit +@ CHECK: .byte target(sbrel) +@ CHECK: ^ + +@ TODO: enable these negative test cases +@ .hword target(sbrel) +@ @ CHECK-SBREL-HWORD: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-HWORD: .hword target(sbrel) +@ @ CHECK-SBREL-HWORD: ^ +@ +@ .short target(sbrel) +@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-SHORT: .short target(sbrel) +@ @ CHECK-SBREL-SHORT: ^ +@ +@ .quad target(sbrel) +@ @ CHECK-SBREL-SHORT: error: relocated expression must be 32-bit +@ @ CHECK-SBREL-SHORT: .quad target(sbrel) +@ @ CHECK-SBREL-SHORT: ^ + + diff --git a/llvm/test/MC/ARM/arm-elf-relocations.s b/llvm/test/MC/ARM/arm-elf-relocations.s index 13d9d2b1e1b..4059591d95b 100644 --- a/llvm/test/MC/ARM/arm-elf-relocations.s +++ b/llvm/test/MC/ARM/arm-elf-relocations.s @@ -25,3 +25,13 @@ @ CHECK: 0x2 R_ARM_ABS16 abs16_1 0x0 @ CHECK: } + .section .text.r_arm_sbrel32 + + .word target(sbrel) + .word target(SBREL) + +@ CHECK: Section {{.*}} .rel.text.r_arm_sbrel32 { +@ CHECK: 0x0 R_ARM_SBREL32 target 0x0 +@ CHECK: 0x4 R_ARM_SBREL32 target 0x0 +@ CHECK: } + |
