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| author | Craig Topper <craig.topper@intel.com> | 2019-05-06 19:50:14 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-06 19:50:14 +0000 |
| commit | ad56843dd780711fea6228fb672d7e56af74cb12 (patch) | |
| tree | 186cd3774ca4673d79f0240a4c4ce640a5b68011 /llvm/test/Transforms/LoopVectorize/conditional-assignment.ll | |
| parent | 3d1128cc9e16db43edf04f4e60df741351f94c2e (diff) | |
| download | bcm5719-llvm-ad56843dd780711fea6228fb672d7e56af74cb12.tar.gz bcm5719-llvm-ad56843dd780711fea6228fb672d7e56af74cb12.zip | |
[SelectionDAG][X86] Support inline assembly returning an mmx register into a type with fewer than 64 bits.
It's possible to use the 'y' mmx constraint with a type narrower than 64-bits.
This patch supports this by bitcasting the mmx type to 64-bits and then
truncating to the desired type.
There are probably other missing type combinations we need to support, but this
is the case we have a bug report for.
Fixes PR41748.
Differential Revision: https://reviews.llvm.org/D61582
llvm-svn: 360069
Diffstat (limited to 'llvm/test/Transforms/LoopVectorize/conditional-assignment.ll')
0 files changed, 0 insertions, 0 deletions
