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authorMehdi Amini <mehdi.amini@apple.com>2015-09-16 05:34:32 +0000
committerMehdi Amini <mehdi.amini@apple.com>2015-09-16 05:34:32 +0000
commitd178f4fc895b432008fcd8a0a49a13d951fecfe4 (patch)
tree19aeac350e85872308d275d4fe8cdce821771d5d /llvm/test/CodeGen
parent8e468d6388ad3a91c2a835529729515c19f74186 (diff)
downloadbcm5719-llvm-d178f4fc895b432008fcd8a0a49a13d951fecfe4.tar.gz
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Make the default triple optional by allowing an empty string
When building LLVM as a (potentially dynamic) library that can be linked against by multiple compilers, the default triple is not really meaningful. We allow to explicitely set it to an empty string when configuring LLVM. In this case, said "target independent" tests in the test suite that are using the default triple are disabled by matching the newly available feature "default_triple". Reviewers: probinson, echristo Differential Revision: http://reviews.llvm.org/D12660 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 247775
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/Generic/lit.local.cfg2
-rw-r--r--llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll1
-rw-r--r--llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll1
-rw-r--r--llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll1
-rw-r--r--llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll1
-rw-r--r--llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll1
-rw-r--r--llvm/test/CodeGen/PowerPC/load-shift-combine.ll1
-rw-r--r--llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll1
-rw-r--r--llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll1
-rw-r--r--llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll1
-rw-r--r--llvm/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll2
-rw-r--r--llvm/test/CodeGen/X86/2010-07-06-DbgCrash.ll1
-rw-r--r--llvm/test/CodeGen/X86/GC/alloc_loop.ll1
-rw-r--r--llvm/test/CodeGen/X86/GC/cg-O0.ll1
-rw-r--r--llvm/test/CodeGen/X86/GC/lower_gcroot.ll1
-rw-r--r--llvm/test/CodeGen/X86/extractelement-shuffle.ll1
-rw-r--r--llvm/test/CodeGen/X86/vshift_scalar.ll1
17 files changed, 18 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Generic/lit.local.cfg b/llvm/test/CodeGen/Generic/lit.local.cfg
index f3f03bd7047..f22d4aabd73 100644
--- a/llvm/test/CodeGen/Generic/lit.local.cfg
+++ b/llvm/test/CodeGen/Generic/lit.local.cfg
@@ -1,3 +1,3 @@
-if 'native' not in config.available_features:
+if not config.target_triple:
config.unsupported = True
diff --git a/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
index fde330321aa..d20e3b05c09 100644
--- a/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
define void @iterative_hash_host_wide_int() {
%zero = alloca i32 ; <i32*> [#uses=2]
diff --git a/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
index c63fd9ae170..3d5fa52d0ab 100644
--- a/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
%struct..0anon = type { i32 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
diff --git a/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
index 0e770985740..c064c273173 100644
--- a/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll
@@ -1,6 +1,7 @@
; RUN: llc < %s -march=ppc64
; RUN: llc < %s -march=ppc32
; RUN: llc < %s
+; REQUIRES: default_triple
define void @bitap() {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
index 9660d450cb4..8536dda0a9b 100644
--- a/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll
@@ -1,6 +1,7 @@
; RUN: llc < %s -march=ppc64
; RUN: llc < %s -march=ppc32
; RUN: llc < %s
+; REQUIRES: default_triple
@qsz.b = external global i1 ; <i1*> [#uses=1]
diff --git a/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
index 4830ca60f9f..aa39dfd0374 100644
--- a/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
+++ b/llvm/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -march=ppc32 -mcpu=g3
; RUN: llc < %s -march=ppc32 -mcpu=g5
; PR1811
+; REQUIRES: default_triple
define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>*
%CONST) {
diff --git a/llvm/test/CodeGen/PowerPC/load-shift-combine.ll b/llvm/test/CodeGen/PowerPC/load-shift-combine.ll
index 8d1f8146db9..3b468572521 100644
--- a/llvm/test/CodeGen/PowerPC/load-shift-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/load-shift-combine.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
; This used to cause a crash. A standard load is converted to a pre-increment
; load. Later the pre-increment load is combined with a subsequent SRL to
diff --git a/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll b/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
index 795d4647a3f..609dbc155ed 100644
--- a/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
+++ b/llvm/test/CodeGen/X86/2006-10-02-BoolRetCrash.ll
@@ -1,5 +1,6 @@
; RUN: llc < %s
; PR933
+; REQUIRES: default_triple
define fastcc i1 @test() {
ret i1 true
diff --git a/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll b/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
index 8bb3dc63a3b..71a560a63ec 100644
--- a/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
+++ b/llvm/test/CodeGen/X86/2009-06-05-VariableIndexInsert.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
define <2 x i64> @_mm_insert_epi16(<2 x i64> %a, i32 %b, i32 %imm) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll b/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
index 92419fcb8b8..e26a8608a49 100644
--- a/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
+++ b/llvm/test/CodeGen/X86/2009-06-06-ConcatVectors.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
define <2 x i64> @_mm_movpi64_pi64(<1 x i64> %a, <1 x i64> %b) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll b/llvm/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
index d6721170d6d..eb077c074bc 100644
--- a/llvm/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
+++ b/llvm/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
@@ -1,4 +1,6 @@
; RUN: llc -O1 < %s
+; REQUIRES: default_triple
+
; ModuleID = 'pr6157.bc'
; formerly crashed in SelectionDAGBuilder
diff --git a/llvm/test/CodeGen/X86/2010-07-06-DbgCrash.ll b/llvm/test/CodeGen/X86/2010-07-06-DbgCrash.ll
index 308d72c481a..5e565a1a667 100644
--- a/llvm/test/CodeGen/X86/2010-07-06-DbgCrash.ll
+++ b/llvm/test/CodeGen/X86/2010-07-06-DbgCrash.ll
@@ -1,4 +1,5 @@
; RUN: llc -O0 -relocation-model pic < %s -o /dev/null
+; REQUIRES: default_triple
; PR7545
@.str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1]
@.str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/GC/alloc_loop.ll b/llvm/test/CodeGen/X86/GC/alloc_loop.ll
index 2a505e80aac..b924e1cee06 100644
--- a/llvm/test/CodeGen/X86/GC/alloc_loop.ll
+++ b/llvm/test/CodeGen/X86/GC/alloc_loop.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
declare i8* @llvm_gc_allocate(i32)
diff --git a/llvm/test/CodeGen/X86/GC/cg-O0.ll b/llvm/test/CodeGen/X86/GC/cg-O0.ll
index b4929425e94..1a390c9eb1c 100644
--- a/llvm/test/CodeGen/X86/GC/cg-O0.ll
+++ b/llvm/test/CodeGen/X86/GC/cg-O0.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s -O0
+; REQUIRES: default_triple
define i32 @main() {
entry:
diff --git a/llvm/test/CodeGen/X86/GC/lower_gcroot.ll b/llvm/test/CodeGen/X86/GC/lower_gcroot.ll
index c2d418ac50e..8cccd78100f 100644
--- a/llvm/test/CodeGen/X86/GC/lower_gcroot.ll
+++ b/llvm/test/CodeGen/X86/GC/lower_gcroot.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
%Env = type i8*
diff --git a/llvm/test/CodeGen/X86/extractelement-shuffle.ll b/llvm/test/CodeGen/X86/extractelement-shuffle.ll
index d1ba9a84580..1b04c41d5c6 100644
--- a/llvm/test/CodeGen/X86/extractelement-shuffle.ll
+++ b/llvm/test/CodeGen/X86/extractelement-shuffle.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
; Examples that exhibits a bug in DAGCombine. The case is triggered by the
; following program. The bug is DAGCombine assumes that the bit convert
diff --git a/llvm/test/CodeGen/X86/vshift_scalar.ll b/llvm/test/CodeGen/X86/vshift_scalar.ll
index 9dd8478caae..87eec3f9e97 100644
--- a/llvm/test/CodeGen/X86/vshift_scalar.ll
+++ b/llvm/test/CodeGen/X86/vshift_scalar.ll
@@ -1,4 +1,5 @@
; RUN: llc < %s
+; REQUIRES: default_triple
; Legalization test that requires scalarizing a vector.
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