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| author | Craig Topper <craig.topper@gmail.com> | 2011-10-14 03:21:46 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-10-14 03:21:46 +0000 |
| commit | 3657fe4b17226da36a0660e40cd03e9d36a5dea0 (patch) | |
| tree | 8c7ea92bf50467ade2fb43fcdbfe5427afb1318b /llvm/test/CodeGen/X86 | |
| parent | d9ea7c8c31705898fc6af0e4dd320c2aeff4f5d9 (diff) | |
| download | bcm5719-llvm-3657fe4b17226da36a0660e40cd03e9d36a5dea0.tar.gz bcm5719-llvm-3657fe4b17226da36a0660e40cd03e9d36a5dea0.zip | |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
llvm-svn: 141939
Diffstat (limited to 'llvm/test/CodeGen/X86')
| -rw-r--r-- | llvm/test/CodeGen/X86/bmi.ll | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/bmi.ll b/llvm/test/CodeGen/X86/bmi.ll new file mode 100644 index 00000000000..e0d1b583aa9 --- /dev/null +++ b/llvm/test/CodeGen/X86/bmi.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s + +define i32 @t1(i32 %x) nounwind { + %tmp = tail call i32 @llvm.cttz.i32( i32 %x ) + ret i32 %tmp +; CHECK: t1: +; CHECK: tzcntl +} + +declare i32 @llvm.cttz.i32(i32) nounwind readnone + +define i16 @t2(i16 %x) nounwind { + %tmp = tail call i16 @llvm.cttz.i16( i16 %x ) + ret i16 %tmp +; CHECK: t2: +; CHECK: tzcntw +} + +declare i16 @llvm.cttz.i16(i16) nounwind readnone + +define i64 @t3(i64 %x) nounwind { + %tmp = tail call i64 @llvm.cttz.i64( i64 %x ) + ret i64 %tmp +; CHECK: t3: +; CHECK: tzcntq +} + +declare i64 @llvm.cttz.i64(i64) nounwind readnone + +define i8 @t4(i8 %x) nounwind { + %tmp = tail call i8 @llvm.cttz.i8( i8 %x ) + ret i8 %tmp +; CHECK: t4: +; CHECK: tzcntw +} + +declare i8 @llvm.cttz.i8(i8) nounwind readnone + |
