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| author | Chandler Carruth <chandlerc@gmail.com> | 2015-02-04 09:06:05 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2015-02-04 09:06:05 +0000 |
| commit | 024cf8efd75c770ffc967bde755d0dec5b9c99e3 (patch) | |
| tree | 8473ba43d88e9cfaed7f8ae2af477e5049a50366 /llvm/test/CodeGen/X86/vector-shuffle-combining.ll | |
| parent | f4a1c33c7cf926ed2ae2eb77e80ce88c849e4727 (diff) | |
| download | bcm5719-llvm-024cf8efd75c770ffc967bde755d0dec5b9c99e3.tar.gz bcm5719-llvm-024cf8efd75c770ffc967bde755d0dec5b9c99e3.zip | |
[x86] Start to introduce bit-masking based blend lowering.
This is the simplest form of bit-math based blending which only fires
when we are blending with zero and is relatively profitable. I've only
enabled this path on very specific lowering strategies. I'm planning to
widen its applicability in subsequent patches, but so far you'll notice
that even though we get fewer shufps instructions, we *still* do the bit
math in the FP execution port. I'm looking into why this is still
happening.
llvm-svn: 228124
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-shuffle-combining.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll index 8261b89c378..ecc9b6e2c59 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining.ll @@ -352,17 +352,13 @@ define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i3 ; SSE2-LABEL: combine_bitwise_ops_test3b: ; SSE2: # BB#0: ; SSE2-NEXT: xorps %xmm1, %xmm0 -; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3] -; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3] +; SSE2-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: combine_bitwise_ops_test3b: ; SSSE3: # BB#0: ; SSSE3-NEXT: xorps %xmm1, %xmm0 -; SSSE3-NEXT: xorps %xmm1, %xmm1 -; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3] -; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3] +; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSSE3-NEXT: retq ; ; SSE41-LABEL: combine_bitwise_ops_test3b: @@ -475,19 +471,13 @@ define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i3 ; SSE2-LABEL: combine_bitwise_ops_test6b: ; SSE2: # BB#0: ; SSE2-NEXT: xorps %xmm1, %xmm0 -; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3] -; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3] -; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: combine_bitwise_ops_test6b: ; SSSE3: # BB#0: ; SSSE3-NEXT: xorps %xmm1, %xmm0 -; SSSE3-NEXT: xorps %xmm1, %xmm1 -; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3] -; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,1,3] -; SSSE3-NEXT: movaps %xmm1, %xmm0 +; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSSE3-NEXT: retq ; ; SSE41-LABEL: combine_bitwise_ops_test6b: |
